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[PULL 27/32] hw/riscv: sifive_u: Add a new property msel for MSEL pin st
From: |
Alistair Francis |
Subject: |
[PULL 27/32] hw/riscv: sifive_u: Add a new property msel for MSEL pin state |
Date: |
Thu, 18 Jun 2020 23:25:13 -0700 |
From: Bin Meng <bin.meng@windriver.com>
On SiFive FU540 SoC, the value stored at physical address 0x1000
stores the MSEL pin state that is used to control the next boot
location that ROM codes jump to.
Add a new property msel to sifive_u machine for this.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1591625864-31494-12-git-send-email-bmeng.cn@gmail.com
Message-Id: <1591625864-31494-12-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
include/hw/riscv/sifive_u.h | 1 +
hw/riscv/sifive_u.c | 7 +++++++
2 files changed, 8 insertions(+)
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index b1399a90a6..f6d10ebfb6 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -63,6 +63,7 @@ typedef struct SiFiveUState {
int fdt_size;
bool start_in_flash;
+ uint32_t msel;
uint32_t serial;
} SiFiveUState;
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 2f9fbb6aa7..ec5cfdae62 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -504,6 +504,13 @@ static void sifive_u_machine_instance_init(Object *obj)
"Set on to tell QEMU's ROM to jump to "
"flash. Otherwise QEMU will jump to DRAM");
+ s->msel = 0;
+ object_property_add(obj, "msel", "uint32",
+ sifive_u_machine_get_uint32_prop,
+ sifive_u_machine_set_uint32_prop, NULL, &s->msel);
+ object_property_set_description(obj, "msel",
+ "Mode Select (MSEL[3:0]) pin state");
+
s->serial = OTP_SERIAL;
object_property_add(obj, "serial", "uint32",
sifive_u_machine_get_uint32_prop,
--
2.27.0
- [PULL 19/32] hw/riscv: sifive_u: Simplify the GEM IRQ connect code a little bit, (continued)
- [PULL 19/32] hw/riscv: sifive_u: Simplify the GEM IRQ connect code a little bit, Alistair Francis, 2020/06/19
- [PULL 08/32] target/riscv: Report errors validating 2nd-stage PTEs, Alistair Francis, 2020/06/19
- [PULL 20/32] hw/riscv: sifive_u: Generate device tree node for OTP, Alistair Francis, 2020/06/19
- [PULL 22/32] hw/riscv: sifive_gpio: Add a new 'ngpio' property, Alistair Francis, 2020/06/19
- [PULL 09/32] target/riscv: Move the hfence instructions to the rvh decode, Alistair Francis, 2020/06/19
- [PULL 23/32] hw/riscv: sifive_u: Hook a GPIO controller, Alistair Francis, 2020/06/19
- [PULL 24/32] hw/riscv: sifive_gpio: Do not blindly trigger output IRQs, Alistair Francis, 2020/06/19
- [PULL 25/32] hw/riscv: sifive_u: Add reset functionality, Alistair Francis, 2020/06/19
- [PULL 26/32] hw/riscv: sifive_u: Rename serial property get/set functions to a generic name, Alistair Francis, 2020/06/19
- [PULL 12/32] hw/char: Initial commit of Ibex UART, Alistair Francis, 2020/06/19
- [PULL 27/32] hw/riscv: sifive_u: Add a new property msel for MSEL pin state,
Alistair Francis <=
- [PULL 28/32] target/riscv: Rename IBEX CPU init routine, Alistair Francis, 2020/06/19
- [PULL 29/32] hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004, Alistair Francis, 2020/06/19
- [PULL 30/32] hw/riscv: sifive_u: Support different boot source per MSEL pin state, Alistair Francis, 2020/06/19
- [PULL 31/32] hw/riscv: sifive_u: Sort the SoC memmap table entries, Alistair Francis, 2020/06/19
- [PULL 32/32] hw/riscv: sifive_u: Add a dummy DDR memory controller device, Alistair Francis, 2020/06/19
- Re: [PULL 00/32] riscv-to-apply queue, no-reply, 2020/06/19
- Re: [PULL 00/32] riscv-to-apply queue, Peter Maydell, 2020/06/19