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Re: [PATCH v7 40/42] target/arm: Cache the Tagged bit for a page in MemT
From: |
Peter Maydell |
Subject: |
Re: [PATCH v7 40/42] target/arm: Cache the Tagged bit for a page in MemTxAttrs |
Date: |
Fri, 19 Jun 2020 15:29:00 +0100 |
On Wed, 3 Jun 2020 at 02:14, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> This "bit" is a particular value of the page's MemAttr.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> v6: Test HCR_EL2.{DC,DCT}; test Stage2 attributes.
> ---
> target/arm/helper.c | 43 +++++++++++++++++++++++++++++++++++--------
> 1 file changed, 35 insertions(+), 8 deletions(-)
>
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index 50717afa4a..74925010ea 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -10875,6 +10875,7 @@ static bool get_phys_addr_lpae(CPUARMState *env,
> target_ulong address,
> uint64_t descaddrmask;
> bool aarch64 = arm_el_is_aa64(env, el);
> bool guarded = false;
> + uint8_t memattr;
>
> /* TODO: This code does not support shareability levels. */
> if (aarch64) {
> @@ -11099,17 +11100,32 @@ static bool get_phys_addr_lpae(CPUARMState *env,
> target_ulong address,
> txattrs->target_tlb_bit0 = true;
> }
>
> - if (cacheattrs != NULL) {
> + if (mmu_idx == ARMMMUIdx_Stage2) {
> + memattr = convert_stage2_attrs(env, extract32(attrs, 0, 4));
> + } else {
> + /* Index into MAIR registers for cache attributes */
> + uint64_t mair = env->cp15.mair_el[el];
> + memattr = extract64(mair, extract32(attrs, 0, 3) * 8, 8);
> + }
> +
> + /* When MTE is enabled, remember Tagged Memory in IOTLB. */
> + if (aarch64 && cpu_isar_feature(aa64_mte, cpu)) {
> if (mmu_idx == ARMMMUIdx_Stage2) {
> - cacheattrs->attrs = convert_stage2_attrs(env,
> - extract32(attrs, 0, 4));
> + /*
> + * Require Normal, I+O Shareable, WB, NT, RA, WA (0xff).
> + * If not, squash stage1 tagged normal setting.
> + */
> + if (memattr != 0xff) {
> + txattrs->target_tlb_bit1 = false;
> + }
Can we implement the effect of stage1+stage2 attrs on whether
the memory location is tagged in the same way it's described in
the Arm ARM, ie by combining the stage1+stage2 attrs and then
looking at the combined result to decide ? In particular, this
code works for the classic attribute-combining logic (where stage2
gets to override only in the more-like-device direction), but
when we get round to implementing ARMv8.4-S2FWB then HCR_EL2.FWB
will allow the stage2 page tables to entirely override stage1
so that we might have memory that is tagged even if stage 1's
attributes said it wasn't.
Currently we do this attribute-combining only for cacheattrs
(the combine_cacheattrs() call) but we could make that deal with
more attributes if we need them for this purpose.
thanks
-- PMM
- [PATCH v7 33/42] target/arm: Add mte helpers for sve scalar + int ff/nf loads, (continued)
- [PATCH v7 33/42] target/arm: Add mte helpers for sve scalar + int ff/nf loads, Richard Henderson, 2020/06/02
- [PATCH v7 36/42] target/arm: Complete TBI clearing for user-only for SVE, Richard Henderson, 2020/06/02
- [PATCH v7 35/42] target/arm: Add mte helpers for sve scatter/gather memory ops, Richard Henderson, 2020/06/02
- [PATCH v7 38/42] target/arm: Set PSTATE.TCO on exception entry, Richard Henderson, 2020/06/02
- [PATCH v7 37/42] target/arm: Implement data cache set allocation tags, Richard Henderson, 2020/06/02
- [PATCH v7 39/42] target/arm: Enable MTE, Richard Henderson, 2020/06/02
- [PATCH v7 40/42] target/arm: Cache the Tagged bit for a page in MemTxAttrs, Richard Henderson, 2020/06/02
- Re: [PATCH v7 40/42] target/arm: Cache the Tagged bit for a page in MemTxAttrs,
Peter Maydell <=
- [PATCH v7 41/42] target/arm: Create tagged ram when MTE is enabled, Richard Henderson, 2020/06/02
- [PATCH v7 42/42] target/arm: Add allocation tag storage for system mode, Richard Henderson, 2020/06/02
- Re: [PATCH v7 00/42] target/arm: Implement ARMv8.5-MemTag, system mode, no-reply, 2020/06/02
- Re: [PATCH v7 00/42] target/arm: Implement ARMv8.5-MemTag, system mode, Peter Maydell, 2020/06/19