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[PULL v2 17/32] hw/riscv: sifive_e: Remove the riscv_ prefix of the mach
From: |
Alistair Francis |
Subject: |
[PULL v2 17/32] hw/riscv: sifive_e: Remove the riscv_ prefix of the machine* and soc* functions |
Date: |
Fri, 19 Jun 2020 09:58:02 -0700 |
From: Bin Meng <bin.meng@windriver.com>
This was done in the virt & sifive_u codes, but sifive_e codes were
missed. Remove the riscv_ prefix of the machine* and soc* functions.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1591625864-31494-2-git-send-email-bmeng.cn@gmail.com
Message-Id: <1591625864-31494-2-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/sifive_e.c | 24 ++++++++++++------------
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index 36486b72d2..01626820bb 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -75,7 +75,7 @@ static const struct MemmapEntry {
[SIFIVE_E_DTIM] = { 0x80000000, 0x4000 }
};
-static void riscv_sifive_e_init(MachineState *machine)
+static void sifive_e_machine_init(MachineState *machine)
{
const struct MemmapEntry *memmap = sifive_e_memmap;
@@ -147,7 +147,7 @@ static void sifive_e_machine_class_init(ObjectClass *oc,
void *data)
MachineClass *mc = MACHINE_CLASS(oc);
mc->desc = "RISC-V Board compatible with SiFive E SDK";
- mc->init = riscv_sifive_e_init;
+ mc->init = sifive_e_machine_init;
mc->max_cpus = 1;
mc->default_cpu_type = SIFIVE_E_CPU;
}
@@ -167,7 +167,7 @@ static void sifive_e_machine_init_register_types(void)
type_init(sifive_e_machine_init_register_types)
-static void riscv_sifive_e_soc_init(Object *obj)
+static void sifive_e_soc_init(Object *obj)
{
MachineState *ms = MACHINE(qdev_get_machine());
SiFiveESoCState *s = RISCV_E_SOC(obj);
@@ -179,7 +179,7 @@ static void riscv_sifive_e_soc_init(Object *obj)
TYPE_SIFIVE_GPIO);
}
-static void riscv_sifive_e_soc_realize(DeviceState *dev, Error **errp)
+static void sifive_e_soc_realize(DeviceState *dev, Error **errp)
{
MachineState *ms = MACHINE(qdev_get_machine());
const struct MemmapEntry *memmap = sifive_e_memmap;
@@ -262,26 +262,26 @@ static void riscv_sifive_e_soc_realize(DeviceState *dev,
Error **errp)
&s->xip_mem);
}
-static void riscv_sifive_e_soc_class_init(ObjectClass *oc, void *data)
+static void sifive_e_soc_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
- dc->realize = riscv_sifive_e_soc_realize;
+ dc->realize = sifive_e_soc_realize;
/* Reason: Uses serial_hds in realize function, thus can't be used twice */
dc->user_creatable = false;
}
-static const TypeInfo riscv_sifive_e_soc_type_info = {
+static const TypeInfo sifive_e_soc_type_info = {
.name = TYPE_RISCV_E_SOC,
.parent = TYPE_DEVICE,
.instance_size = sizeof(SiFiveESoCState),
- .instance_init = riscv_sifive_e_soc_init,
- .class_init = riscv_sifive_e_soc_class_init,
+ .instance_init = sifive_e_soc_init,
+ .class_init = sifive_e_soc_class_init,
};
-static void riscv_sifive_e_soc_register_types(void)
+static void sifive_e_soc_register_types(void)
{
- type_register_static(&riscv_sifive_e_soc_type_info);
+ type_register_static(&sifive_e_soc_type_info);
}
-type_init(riscv_sifive_e_soc_register_types)
+type_init(sifive_e_soc_register_types)
--
2.27.0
- [PULL v2 14/32] riscv/opentitan: Connect the PLIC device, (continued)
- [PULL v2 14/32] riscv/opentitan: Connect the PLIC device, Alistair Francis, 2020/06/19
- [PULL v2 15/32] riscv/opentitan: Connect the UART device, Alistair Francis, 2020/06/19
- [PULL v2 04/32] riscv: Generalize CPU init routine for the gcsu CPU, Alistair Francis, 2020/06/19
- [PULL v2 06/32] riscv: Keep the CPU init routine names consistent, Alistair Francis, 2020/06/19
- [PULL v2 03/32] riscv: Generalize CPU init routine for the base CPU, Alistair Francis, 2020/06/19
- [PULL v2 19/32] hw/riscv: sifive_u: Simplify the GEM IRQ connect code a little bit, Alistair Francis, 2020/06/19
- [PULL v2 02/32] sifive_e: Support the revB machine, Alistair Francis, 2020/06/19
- [PULL v2 16/32] target/riscv: Use a smaller guess size for no-MMU PMP, Alistair Francis, 2020/06/19
- [PULL v2 05/32] riscv: Generalize CPU init routine for the imacu CPU, Alistair Francis, 2020/06/19
- [PULL v2 08/32] target/riscv: Report errors validating 2nd-stage PTEs, Alistair Francis, 2020/06/19
- [PULL v2 17/32] hw/riscv: sifive_e: Remove the riscv_ prefix of the machine* and soc* functions,
Alistair Francis <=
- [PULL v2 22/32] hw/riscv: sifive_gpio: Add a new 'ngpio' property, Alistair Francis, 2020/06/19
- [PULL v2 21/32] hw/riscv: sifive_gpio: Clean up the codes, Alistair Francis, 2020/06/19
- [PULL v2 24/32] hw/riscv: sifive_gpio: Do not blindly trigger output IRQs, Alistair Francis, 2020/06/19
- [PULL v2 18/32] hw/riscv: opentitan: Remove the riscv_ prefix of the machine* and soc* functions, Alistair Francis, 2020/06/19
- [PULL v2 20/32] hw/riscv: sifive_u: Generate device tree node for OTP, Alistair Francis, 2020/06/19
- [PULL v2 23/32] hw/riscv: sifive_u: Hook a GPIO controller, Alistair Francis, 2020/06/19
- [PULL v2 07/32] target/riscv: Set access as data_load when validating stage-2 PTEs, Alistair Francis, 2020/06/19
- [PULL v2 10/32] target/riscv: Implement checks for hfence, Alistair Francis, 2020/06/19
- [PULL v2 11/32] riscv/opentitan: Fix the ROM size, Alistair Francis, 2020/06/19
- [PULL v2 09/32] target/riscv: Move the hfence instructions to the rvh decode, Alistair Francis, 2020/06/19