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[PULL v2 31/32] hw/riscv: sifive_u: Sort the SoC memmap table entries
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From: |
Alistair Francis |
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Subject: |
[PULL v2 31/32] hw/riscv: sifive_u: Sort the SoC memmap table entries |
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Date: |
Fri, 19 Jun 2020 09:58:16 -0700 |
From: Bin Meng <bin.meng@windriver.com>
Move the flash and DRAM to the end of the SoC memmap table.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1592268641-7478-5-git-send-email-bmeng.cn@gmail.com
Message-Id: <1592268641-7478-5-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/sifive_u.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index eb767aa863..b9d0a6901a 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -80,10 +80,10 @@ static const struct MemmapEntry {
[SIFIVE_U_UART1] = { 0x10011000, 0x1000 },
[SIFIVE_U_GPIO] = { 0x10060000, 0x1000 },
[SIFIVE_U_OTP] = { 0x10070000, 0x1000 },
- [SIFIVE_U_FLASH0] = { 0x20000000, 0x10000000 },
- [SIFIVE_U_DRAM] = { 0x80000000, 0x0 },
[SIFIVE_U_GEM] = { 0x10090000, 0x2000 },
[SIFIVE_U_GEM_MGMT] = { 0x100a0000, 0x1000 },
+ [SIFIVE_U_FLASH0] = { 0x20000000, 0x10000000 },
+ [SIFIVE_U_DRAM] = { 0x80000000, 0x0 },
};
#define OTP_SERIAL 1
--
2.27.0
- [PULL v2 11/32] riscv/opentitan: Fix the ROM size, (continued)
- [PULL v2 11/32] riscv/opentitan: Fix the ROM size, Alistair Francis, 2020/06/19
- [PULL v2 09/32] target/riscv: Move the hfence instructions to the rvh decode, Alistair Francis, 2020/06/19
- [PULL v2 12/32] hw/char: Initial commit of Ibex UART, Alistair Francis, 2020/06/19
- [PULL v2 25/32] hw/riscv: sifive_u: Add reset functionality, Alistair Francis, 2020/06/19
- [PULL v2 26/32] hw/riscv: sifive_u: Rename serial property get/set functions to a generic name, Alistair Francis, 2020/06/19
- [PULL v2 27/32] hw/riscv: sifive_u: Add a new property msel for MSEL pin state, Alistair Francis, 2020/06/19
- [PULL v2 13/32] hw/intc: Initial commit of lowRISC Ibex PLIC, Alistair Francis, 2020/06/19
- [PULL v2 28/32] target/riscv: Rename IBEX CPU init routine, Alistair Francis, 2020/06/19
- [PULL v2 29/32] hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004, Alistair Francis, 2020/06/19
- [PULL v2 30/32] hw/riscv: sifive_u: Support different boot source per MSEL pin state, Alistair Francis, 2020/06/19
- [PULL v2 31/32] hw/riscv: sifive_u: Sort the SoC memmap table entries,
Alistair Francis <=
- [PULL v2 32/32] hw/riscv: sifive_u: Add a dummy DDR memory controller device, Alistair Francis, 2020/06/19
- Re: [PULL v2 00/32] riscv-to-apply queue, no-reply, 2020/06/19
- Re: [PULL v2 00/32] riscv-to-apply queue, Peter Maydell, 2020/06/22