[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH v9 31/46] target/arm: Tidy trans_LD1R_zpri
From: |
Richard Henderson |
Subject: |
[PATCH v9 31/46] target/arm: Tidy trans_LD1R_zpri |
Date: |
Thu, 25 Jun 2020 20:31:29 -0700 |
Move the variable declarations to the top of the function,
but do not create a new label before sve_access_check.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
v8: Split out from previous patch (pmm).
---
target/arm/translate-sve.c | 12 +++++++-----
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index 4fa521989d..a3a0b98fbc 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -4883,17 +4883,19 @@ static bool trans_LD1RQ_zpri(DisasContext *s,
arg_rpri_load *a)
/* Load and broadcast element. */
static bool trans_LD1R_zpri(DisasContext *s, arg_rpri_load *a)
{
- if (!sve_access_check(s)) {
- return true;
- }
-
unsigned vsz = vec_full_reg_size(s);
unsigned psz = pred_full_reg_size(s);
unsigned esz = dtype_esz[a->dtype];
unsigned msz = dtype_msz(a->dtype);
- TCGLabel *over = gen_new_label();
+ TCGLabel *over;
TCGv_i64 temp, clean_addr;
+ if (!sve_access_check(s)) {
+ return true;
+ }
+
+ over = gen_new_label();
+
/* If the guarding predicate has no bits set, no load occurs. */
if (psz <= 8) {
/* Reduce the pred_esz_masks value simply to reduce the
--
2.25.1
- [PATCH v9 22/46] target/arm: Move regime_tcr to internals.h, (continued)
- [PATCH v9 22/46] target/arm: Move regime_tcr to internals.h, Richard Henderson, 2020/06/25
- [PATCH v9 23/46] target/arm: Add gen_mte_check1, Richard Henderson, 2020/06/25
- [PATCH v9 24/46] target/arm: Add gen_mte_checkN, Richard Henderson, 2020/06/25
- [PATCH v9 25/46] target/arm: Implement helper_mte_check1, Richard Henderson, 2020/06/25
- [PATCH v9 26/46] target/arm: Implement helper_mte_checkN, Richard Henderson, 2020/06/25
- [PATCH v9 27/46] target/arm: Add helper_mte_check_zva, Richard Henderson, 2020/06/25
- [PATCH v9 28/46] target/arm: Use mte_checkN for sve unpredicated loads, Richard Henderson, 2020/06/25
- [PATCH v9 30/46] target/arm: Use mte_check1 for sve LD1R, Richard Henderson, 2020/06/25
- [PATCH v9 29/46] target/arm: Use mte_checkN for sve unpredicated stores, Richard Henderson, 2020/06/25
- [PATCH v9 32/46] target/arm: Add arm_tlb_bti_gp, Richard Henderson, 2020/06/25
- [PATCH v9 31/46] target/arm: Tidy trans_LD1R_zpri,
Richard Henderson <=
- [PATCH v9 33/46] target/arm: Add mte helpers for sve scalar + int loads, Richard Henderson, 2020/06/25
- [PATCH v9 34/46] target/arm: Add mte helpers for sve scalar + int stores, Richard Henderson, 2020/06/25
- [PATCH v9 35/46] target/arm: Add mte helpers for sve scalar + int ff/nf loads, Richard Henderson, 2020/06/25
- [PATCH v9 36/46] target/arm: Handle TBI for sve scalar + int memory ops, Richard Henderson, 2020/06/25
- [PATCH v9 39/46] target/arm: Implement data cache set allocation tags, Richard Henderson, 2020/06/25
- [PATCH v9 37/46] target/arm: Add mte helpers for sve scatter/gather memory ops, Richard Henderson, 2020/06/25
- [PATCH v9 38/46] target/arm: Complete TBI clearing for user-only for SVE, Richard Henderson, 2020/06/25
- [PATCH v9 40/46] target/arm: Set PSTATE.TCO on exception entry, Richard Henderson, 2020/06/25
- [PATCH v9 41/46] target/arm: Always pass cacheattr to get_phys_addr, Richard Henderson, 2020/06/25
- [PATCH v9 42/46] target/arm: Cache the Tagged bit for a page in MemTxAttrs, Richard Henderson, 2020/06/25