Re: [PATCH v9 00/46] target/arm: Implement ARMv8.5-MemTag, system mode

[no-reply]

Patchew URL: 
20200626033144.790098-1-richard.henderson@linaro.org/">https://patchew.org/QEMU/20200626033144.790098-1-richard.henderson@linaro.org/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Subject: [PATCH v9 00/46] target/arm: Implement ARMv8.5-MemTag, system mode
Type: series
Message-id: 20200626033144.790098-1-richard.henderson@linaro.org

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

From https://github.com/patchew-project/qemu
 - [tag update]      
patchew/20200626033144.790098-1-richard.henderson@linaro.org -> 
patchew/20200626033144.790098-1-richard.henderson@linaro.org
Switched to a new branch 'test'
ea14124 target/arm: Add arm,armv8.5-memtag to dtb
026e589 target/arm: Enable MTE
fa6356a target/arm: Add allocation tag storage for system mode
f2fc923 target/arm: Create tagged ram when MTE is enabled
712e523 target/arm: Cache the Tagged bit for a page in MemTxAttrs
1c7fdd5 target/arm: Always pass cacheattr to get_phys_addr
945b78b target/arm: Set PSTATE.TCO on exception entry
c922cc0 target/arm: Implement data cache set allocation tags
bad8858 target/arm: Complete TBI clearing for user-only for SVE
eb44aa0 target/arm: Add mte helpers for sve scatter/gather memory ops
fd47bb8 target/arm: Handle TBI for sve scalar + int memory ops
d101c09 target/arm: Add mte helpers for sve scalar + int ff/nf loads
7b66cd4 target/arm: Add mte helpers for sve scalar + int stores
460243b target/arm: Add mte helpers for sve scalar + int loads
0b0dbb6 target/arm: Add arm_tlb_bti_gp
942f9c5 target/arm: Tidy trans_LD1R_zpri
a2965d5 target/arm: Use mte_check1 for sve LD1R
70061de target/arm: Use mte_checkN for sve unpredicated stores
4d333a6 target/arm: Use mte_checkN for sve unpredicated loads
43f282a target/arm: Add helper_mte_check_zva
c6f0339 target/arm: Implement helper_mte_checkN
4bd0d5f target/arm: Implement helper_mte_check1
edcfda1 target/arm: Add gen_mte_checkN
c7a4e6b target/arm: Add gen_mte_check1
f739caf target/arm: Move regime_tcr to internals.h
dd91a4a target/arm: Move regime_el to internals.h
4b498b4 target/arm: Implement the access tag cache flushes
045e5a9 target/arm: Implement the LDGM, STGM, STZGM instructions
9ee3f3a target/arm: Simplify DC_ZVA
e4b03e8 target/arm: Restrict the values of DCZID.BS under TCG
47691b4 target/arm: Implement the STGP instruction
72b11e0 target/arm: Implement LDG, STG, ST2G instructions
042564c target/arm: Define arm_cpu_do_unaligned_access for user-only
9b9d7e8 target/arm: Implement the SUBP instruction
9563b5f target/arm: Implement the GMI instruction
bff6771 target/arm: Implement the ADDG, SUBG instructions
d0e93a7 target/arm: Revise decoding for disas_add_sub_imm
515496c target/arm: Implement the IRG instruction
e7782e6 target/arm: Add MTE bits to tb_flags
11bfa4a target/arm: Add MTE system registers
6052630 target/arm: Add DISAS_UPDATE_NOCHAIN
1932e01 target/arm: Rename DISAS_UPDATE to DISAS_UPDATE_EXIT
c9ebd4b target/arm: Add support for MTE to HCR_EL2 and SCR_EL3
e3eae8a target/arm: Add support for MTE to SCTLR_ELx
cd16db3 target/arm: Improve masking of SCR RES0 bits
2c4afe3 target/arm: Add isar tests for mte

=== OUTPUT BEGIN ===
1/46 Checking commit 2c4afe349858 (target/arm: Add isar tests for mte)
2/46 Checking commit cd16db3d6f0c (target/arm: Improve masking of SCR RES0 bits)
3/46 Checking commit e3eae8ac6f72 (target/arm: Add support for MTE to SCTLR_ELx)
4/46 Checking commit c9ebd4b7538b (target/arm: Add support for MTE to HCR_EL2 
and SCR_EL3)
5/46 Checking commit 1932e0177665 (target/arm: Rename DISAS_UPDATE to 
DISAS_UPDATE_EXIT)
6/46 Checking commit 60526300071c (target/arm: Add DISAS_UPDATE_NOCHAIN)
7/46 Checking commit 11bfa4af1833 (target/arm: Add MTE system registers)
8/46 Checking commit e7782e6fcc94 (target/arm: Add MTE bits to tb_flags)
9/46 Checking commit 515496c0a8bf (target/arm: Implement the IRG instruction)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#45: 
new file mode 100644

total: 0 errors, 1 warnings, 120 lines checked

Patch 9/46 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/46 Checking commit d0e93a779105 (target/arm: Revise decoding for 
disas_add_sub_imm)
11/46 Checking commit bff67715f6b3 (target/arm: Implement the ADDG, SUBG 
instructions)
12/46 Checking commit 9563b5f54347 (target/arm: Implement the GMI instruction)
13/46 Checking commit 9b9d7e8534b3 (target/arm: Implement the SUBP instruction)
14/46 Checking commit 042564cfe6c3 (target/arm: Define 
arm_cpu_do_unaligned_access for user-only)
15/46 Checking commit 72b11e0ba319 (target/arm: Implement LDG, STG, ST2G 
instructions)
16/46 Checking commit 47691b45881c (target/arm: Implement the STGP instruction)
17/46 Checking commit e4b03e8f5284 (target/arm: Restrict the values of DCZID.BS 
under TCG)
18/46 Checking commit 9ee3f3a3393c (target/arm: Simplify DC_ZVA)
19/46 Checking commit 045e5a90e6bc (target/arm: Implement the LDGM, STGM, STZGM 
instructions)
20/46 Checking commit 4b498b4743c1 (target/arm: Implement the access tag cache 
flushes)
21/46 Checking commit dd91a4ac8cb5 (target/arm: Move regime_el to internals.h)
22/46 Checking commit f739caf553f2 (target/arm: Move regime_tcr to internals.h)
23/46 Checking commit c7a4e6bccd6a (target/arm: Add gen_mte_check1)
24/46 Checking commit edcfda13df2d (target/arm: Add gen_mte_checkN)
25/46 Checking commit 4bd0d5fb2060 (target/arm: Implement helper_mte_check1)
26/46 Checking commit c6f033940b2e (target/arm: Implement helper_mte_checkN)
27/46 Checking commit 43f282a31501 (target/arm: Add helper_mte_check_zva)
28/46 Checking commit 4d333a670294 (target/arm: Use mte_checkN for sve 
unpredicated loads)
29/46 Checking commit 70061dee2c97 (target/arm: Use mte_checkN for sve 
unpredicated stores)
30/46 Checking commit a2965d554b55 (target/arm: Use mte_check1 for sve LD1R)
31/46 Checking commit 942f9c5c274f (target/arm: Tidy trans_LD1R_zpri)
32/46 Checking commit 0b0dbb6dabac (target/arm: Add arm_tlb_bti_gp)
33/46 Checking commit 460243b91717 (target/arm: Add mte helpers for sve scalar 
+ int loads)
34/46 Checking commit 7b66cd4ba344 (target/arm: Add mte helpers for sve scalar 
+ int stores)
35/46 Checking commit d101c0961f2e (target/arm: Add mte helpers for sve scalar 
+ int ff/nf loads)
36/46 Checking commit fd47bb8822d5 (target/arm: Handle TBI for sve scalar + int 
memory ops)
37/46 Checking commit eb44aa08aa52 (target/arm: Add mte helpers for sve 
scatter/gather memory ops)
38/46 Checking commit bad88583af69 (target/arm: Complete TBI clearing for 
user-only for SVE)
ERROR: spaces required around that '*' (ctx:VxV)
#57: FILE: target/arm/sve_helper.c:3978:
+        (TYPEM)*(TYPEE *)(vd + H(reg_off)), ra);                            \
                ^

total: 1 errors, 0 warnings, 57 lines checked

Patch 38/46 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

39/46 Checking commit c922cc099458 (target/arm: Implement data cache set 
allocation tags)
40/46 Checking commit 945b78b9b5ce (target/arm: Set PSTATE.TCO on exception 
entry)
41/46 Checking commit 1c7fdd591266 (target/arm: Always pass cacheattr to 
get_phys_addr)
42/46 Checking commit 712e523bf512 (target/arm: Cache the Tagged bit for a page 
in MemTxAttrs)
43/46 Checking commit f2fc923a1075 (target/arm: Create tagged ram when MTE is 
enabled)
44/46 Checking commit fa6356aadd32 (target/arm: Add allocation tag storage for 
system mode)
45/46 Checking commit 026e5898ca2d (target/arm: Enable MTE)
46/46 Checking commit ea141247b110 (target/arm: Add arm,armv8.5-memtag to dtb)
=== OUTPUT END ===

Test command exited with code: 1


The full log is available at
20200626033144.790098-1-richard.henderson@linaro.org/testing.checkpatch/?type=message">http://patchew.org/logs/20200626033144.790098-1-richard.henderson@linaro.org/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [https://patchew.org/].
Please send your feedback to patchew-devel@redhat.com