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[PULL 24/57] target/arm: Implement the GMI instruction
From: |
Peter Maydell |
Subject: |
[PULL 24/57] target/arm: Implement the GMI instruction |
Date: |
Fri, 26 Jun 2020 16:13:51 +0100 |
From: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200626033144.790098-13-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/translate-a64.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 2ec02c8a5f3..ee9dfa8e439 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -5346,6 +5346,21 @@ static void disas_data_proc_2src(DisasContext *s,
uint32_t insn)
cpu_reg_sp(s, rn));
}
break;
+ case 5: /* GMI */
+ if (sf == 0 || !dc_isar_feature(aa64_mte_insn_reg, s)) {
+ goto do_unallocated;
+ } else {
+ TCGv_i64 t1 = tcg_const_i64(1);
+ TCGv_i64 t2 = tcg_temp_new_i64();
+
+ tcg_gen_extract_i64(t2, cpu_reg_sp(s, rn), 56, 4);
+ tcg_gen_shl_i64(t1, t1, t2);
+ tcg_gen_or_i64(cpu_reg(s, rd), cpu_reg(s, rm), t1);
+
+ tcg_temp_free_i64(t1);
+ tcg_temp_free_i64(t2);
+ }
+ break;
case 8: /* LSLV */
handle_shift_reg(s, A64_SHIFT_TYPE_LSL, sf, rm, rn, rd);
break;
--
2.20.1
- [PULL 11/57] hw/misc/pca9552: Trace GPIO change events, (continued)
- [PULL 11/57] hw/misc/pca9552: Trace GPIO change events, Peter Maydell, 2020/06/26
- [PULL 15/57] target/arm: Add support for MTE to SCTLR_ELx, Peter Maydell, 2020/06/26
- [PULL 14/57] target/arm: Improve masking of SCR RES0 bits, Peter Maydell, 2020/06/26
- [PULL 16/57] target/arm: Add support for MTE to HCR_EL2 and SCR_EL3, Peter Maydell, 2020/06/26
- [PULL 13/57] target/arm: Add isar tests for mte, Peter Maydell, 2020/06/26
- [PULL 17/57] target/arm: Rename DISAS_UPDATE to DISAS_UPDATE_EXIT, Peter Maydell, 2020/06/26
- [PULL 21/57] target/arm: Implement the IRG instruction, Peter Maydell, 2020/06/26
- [PULL 18/57] target/arm: Add DISAS_UPDATE_NOCHAIN, Peter Maydell, 2020/06/26
- [PULL 19/57] target/arm: Add MTE system registers, Peter Maydell, 2020/06/26
- [PULL 20/57] target/arm: Add MTE bits to tb_flags, Peter Maydell, 2020/06/26
- [PULL 24/57] target/arm: Implement the GMI instruction,
Peter Maydell <=
- [PULL 22/57] target/arm: Revise decoding for disas_add_sub_imm, Peter Maydell, 2020/06/26
- [PULL 23/57] target/arm: Implement the ADDG, SUBG instructions, Peter Maydell, 2020/06/26
- [PULL 25/57] target/arm: Implement the SUBP instruction, Peter Maydell, 2020/06/26
- [PULL 26/57] target/arm: Define arm_cpu_do_unaligned_access for user-only, Peter Maydell, 2020/06/26
- [PULL 28/57] target/arm: Implement the STGP instruction, Peter Maydell, 2020/06/26
- [PULL 29/57] target/arm: Restrict the values of DCZID.BS under TCG, Peter Maydell, 2020/06/26
- [PULL 27/57] target/arm: Implement LDG, STG, ST2G instructions, Peter Maydell, 2020/06/26
- [PULL 30/57] target/arm: Simplify DC_ZVA, Peter Maydell, 2020/06/26
- [PULL 31/57] target/arm: Implement the LDGM, STGM, STZGM instructions, Peter Maydell, 2020/06/26
- [PULL 32/57] target/arm: Implement the access tag cache flushes, Peter Maydell, 2020/06/26