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[PULL 33/57] target/arm: Move regime_el to internals.h
From: |
Peter Maydell |
Subject: |
[PULL 33/57] target/arm: Move regime_el to internals.h |
Date: |
Fri, 26 Jun 2020 16:14:00 +0100 |
From: Richard Henderson <richard.henderson@linaro.org>
We will shortly need this in mte_helper.c as well.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200626033144.790098-22-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/internals.h | 36 ++++++++++++++++++++++++++++++++++++
target/arm/helper.c | 36 ------------------------------------
2 files changed, 36 insertions(+), 36 deletions(-)
diff --git a/target/arm/internals.h b/target/arm/internals.h
index 5c69d4e5a56..c36fcb151b7 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -913,6 +913,42 @@ static inline bool regime_is_pan(CPUARMState *env,
ARMMMUIdx mmu_idx)
}
}
+/* Return the exception level which controls this address translation regime */
+static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx)
+{
+ switch (mmu_idx) {
+ case ARMMMUIdx_E20_0:
+ case ARMMMUIdx_E20_2:
+ case ARMMMUIdx_E20_2_PAN:
+ case ARMMMUIdx_Stage2:
+ case ARMMMUIdx_E2:
+ return 2;
+ case ARMMMUIdx_SE3:
+ return 3;
+ case ARMMMUIdx_SE10_0:
+ return arm_el_is_aa64(env, 3) ? 1 : 3;
+ case ARMMMUIdx_SE10_1:
+ case ARMMMUIdx_SE10_1_PAN:
+ case ARMMMUIdx_Stage1_E0:
+ case ARMMMUIdx_Stage1_E1:
+ case ARMMMUIdx_Stage1_E1_PAN:
+ case ARMMMUIdx_E10_0:
+ case ARMMMUIdx_E10_1:
+ case ARMMMUIdx_E10_1_PAN:
+ case ARMMMUIdx_MPrivNegPri:
+ case ARMMMUIdx_MUserNegPri:
+ case ARMMMUIdx_MPriv:
+ case ARMMMUIdx_MUser:
+ case ARMMMUIdx_MSPrivNegPri:
+ case ARMMMUIdx_MSUserNegPri:
+ case ARMMMUIdx_MSPriv:
+ case ARMMMUIdx_MSUser:
+ return 1;
+ default:
+ g_assert_not_reached();
+ }
+}
+
/* Return the FSR value for a debug exception (watchpoint, hardware
* breakpoint or BKPT insn) targeting the specified exception level.
*/
diff --git a/target/arm/helper.c b/target/arm/helper.c
index d8c31d03dad..d14313de664 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -9793,42 +9793,6 @@ void arm_cpu_do_interrupt(CPUState *cs)
}
#endif /* !CONFIG_USER_ONLY */
-/* Return the exception level which controls this address translation regime */
-static uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx)
-{
- switch (mmu_idx) {
- case ARMMMUIdx_E20_0:
- case ARMMMUIdx_E20_2:
- case ARMMMUIdx_E20_2_PAN:
- case ARMMMUIdx_Stage2:
- case ARMMMUIdx_E2:
- return 2;
- case ARMMMUIdx_SE3:
- return 3;
- case ARMMMUIdx_SE10_0:
- return arm_el_is_aa64(env, 3) ? 1 : 3;
- case ARMMMUIdx_SE10_1:
- case ARMMMUIdx_SE10_1_PAN:
- case ARMMMUIdx_Stage1_E0:
- case ARMMMUIdx_Stage1_E1:
- case ARMMMUIdx_Stage1_E1_PAN:
- case ARMMMUIdx_E10_0:
- case ARMMMUIdx_E10_1:
- case ARMMMUIdx_E10_1_PAN:
- case ARMMMUIdx_MPrivNegPri:
- case ARMMMUIdx_MUserNegPri:
- case ARMMMUIdx_MPriv:
- case ARMMMUIdx_MUser:
- case ARMMMUIdx_MSPrivNegPri:
- case ARMMMUIdx_MSUserNegPri:
- case ARMMMUIdx_MSPriv:
- case ARMMMUIdx_MSUser:
- return 1;
- default:
- g_assert_not_reached();
- }
-}
-
uint64_t arm_sctlr(CPUARMState *env, int el)
{
/* Only EL0 needs to be adjusted for EL1&0 or EL2&0. */
--
2.20.1
- [PULL 22/57] target/arm: Revise decoding for disas_add_sub_imm, (continued)
- [PULL 22/57] target/arm: Revise decoding for disas_add_sub_imm, Peter Maydell, 2020/06/26
- [PULL 23/57] target/arm: Implement the ADDG, SUBG instructions, Peter Maydell, 2020/06/26
- [PULL 25/57] target/arm: Implement the SUBP instruction, Peter Maydell, 2020/06/26
- [PULL 26/57] target/arm: Define arm_cpu_do_unaligned_access for user-only, Peter Maydell, 2020/06/26
- [PULL 28/57] target/arm: Implement the STGP instruction, Peter Maydell, 2020/06/26
- [PULL 29/57] target/arm: Restrict the values of DCZID.BS under TCG, Peter Maydell, 2020/06/26
- [PULL 27/57] target/arm: Implement LDG, STG, ST2G instructions, Peter Maydell, 2020/06/26
- [PULL 30/57] target/arm: Simplify DC_ZVA, Peter Maydell, 2020/06/26
- [PULL 31/57] target/arm: Implement the LDGM, STGM, STZGM instructions, Peter Maydell, 2020/06/26
- [PULL 32/57] target/arm: Implement the access tag cache flushes, Peter Maydell, 2020/06/26
- [PULL 33/57] target/arm: Move regime_el to internals.h,
Peter Maydell <=
- [PULL 34/57] target/arm: Move regime_tcr to internals.h, Peter Maydell, 2020/06/26
- [PULL 35/57] target/arm: Add gen_mte_check1, Peter Maydell, 2020/06/26
- [PULL 37/57] target/arm: Implement helper_mte_check1, Peter Maydell, 2020/06/26
- [PULL 36/57] target/arm: Add gen_mte_checkN, Peter Maydell, 2020/06/26
- [PULL 41/57] target/arm: Use mte_checkN for sve unpredicated stores, Peter Maydell, 2020/06/26
- [PULL 38/57] target/arm: Implement helper_mte_checkN, Peter Maydell, 2020/06/26
- [PULL 40/57] target/arm: Use mte_checkN for sve unpredicated loads, Peter Maydell, 2020/06/26
- [PULL 42/57] target/arm: Use mte_check1 for sve LD1R, Peter Maydell, 2020/06/26
- [PULL 43/57] target/arm: Tidy trans_LD1R_zpri, Peter Maydell, 2020/06/26
- [PULL 44/57] target/arm: Add arm_tlb_bti_gp, Peter Maydell, 2020/06/26