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[PATCH 4/6] target/riscv: check before allocating TCG temps
From: |
LIU Zhiwei |
Subject: |
[PATCH 4/6] target/riscv: check before allocating TCG temps |
Date: |
Sat, 27 Jun 2020 04:59:15 +0800 |
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
target/riscv/insn_trans/trans_rvd.inc.c | 8 ++++----
target/riscv/insn_trans/trans_rvf.inc.c | 8 ++++----
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvd.inc.c
b/target/riscv/insn_trans/trans_rvd.inc.c
index cd73a326f4..c0f4a0c789 100644
--- a/target/riscv/insn_trans/trans_rvd.inc.c
+++ b/target/riscv/insn_trans/trans_rvd.inc.c
@@ -20,10 +20,10 @@
static bool trans_fld(DisasContext *ctx, arg_fld *a)
{
- TCGv t0 = tcg_temp_new();
- gen_get_gpr(t0, a->rs1);
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVD);
+ TCGv t0 = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
tcg_gen_addi_tl(t0, t0, a->imm);
tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEQ);
@@ -35,10 +35,10 @@ static bool trans_fld(DisasContext *ctx, arg_fld *a)
static bool trans_fsd(DisasContext *ctx, arg_fsd *a)
{
- TCGv t0 = tcg_temp_new();
- gen_get_gpr(t0, a->rs1);
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVD);
+ TCGv t0 = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
tcg_gen_addi_tl(t0, t0, a->imm);
tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEQ);
diff --git a/target/riscv/insn_trans/trans_rvf.inc.c
b/target/riscv/insn_trans/trans_rvf.inc.c
index a3d74dd83d..04bc8e5cb5 100644
--- a/target/riscv/insn_trans/trans_rvf.inc.c
+++ b/target/riscv/insn_trans/trans_rvf.inc.c
@@ -25,10 +25,10 @@
static bool trans_flw(DisasContext *ctx, arg_flw *a)
{
- TCGv t0 = tcg_temp_new();
- gen_get_gpr(t0, a->rs1);
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
+ TCGv t0 = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
tcg_gen_addi_tl(t0, t0, a->imm);
tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEUL);
@@ -41,11 +41,11 @@ static bool trans_flw(DisasContext *ctx, arg_flw *a)
static bool trans_fsw(DisasContext *ctx, arg_fsw *a)
{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVF);
TCGv t0 = tcg_temp_new();
gen_get_gpr(t0, a->rs1);
- REQUIRE_FPU;
- REQUIRE_EXT(ctx, RVF);
tcg_gen_addi_tl(t0, t0, a->imm);
tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEUL);
--
2.23.0
- [PATCH 0/6] target/riscv: NaN-boxing for multiple precison, LIU Zhiwei, 2020/06/26
- [PATCH 1/6] target/riscv: move gen_nanbox_fpr to translate.c, LIU Zhiwei, 2020/06/26
- [PATCH 2/6] target/riscv: NaN-boxing compute, sign-injection and convert instructions., LIU Zhiwei, 2020/06/26
- [PATCH 3/6] target/riscv: Check for LEGAL NaN-boxing, LIU Zhiwei, 2020/06/26
- [PATCH 4/6] target/riscv: check before allocating TCG temps,
LIU Zhiwei <=
- [PATCH 5/6] target/riscv: Flush not valid NaN-boxing input to canonical NaN, LIU Zhiwei, 2020/06/26
- [PATCH 6/6] target/riscv: clean up fmv.w.x, LIU Zhiwei, 2020/06/26
- Re: [PATCH 0/6] target/riscv: NaN-boxing for multiple precison, no-reply, 2020/06/26