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[PULL 01/63] riscv: plic: Honour source priorities
From: |
Alistair Francis |
Subject: |
[PULL 01/63] riscv: plic: Honour source priorities |
Date: |
Fri, 26 Jun 2020 14:43:08 -0700 |
From: Jessica Clarke <jrtc27@jrtc27.com>
The source priorities can be used to order sources with respect to other
sources, not just as a way to enable/disable them based off a threshold.
We must therefore always claim the highest-priority source, rather than
the first source we find.
Signed-off-by: Jessica Clarke <jrtc27@jrtc27.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20200618202343.20455-1-jrtc27@jrtc27.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/sifive_plic.c | 17 ++++++++++++-----
1 file changed, 12 insertions(+), 5 deletions(-)
diff --git a/hw/riscv/sifive_plic.c b/hw/riscv/sifive_plic.c
index 4f216c5585..d91e82b8ab 100644
--- a/hw/riscv/sifive_plic.c
+++ b/hw/riscv/sifive_plic.c
@@ -166,6 +166,9 @@ static void sifive_plic_update(SiFivePLICState *plic)
static uint32_t sifive_plic_claim(SiFivePLICState *plic, uint32_t addrid)
{
int i, j;
+ uint32_t max_irq = 0;
+ uint32_t max_prio = plic->target_priority[addrid];
+
for (i = 0; i < plic->bitfield_words; i++) {
uint32_t pending_enabled_not_claimed =
(plic->pending[i] & ~plic->claimed[i]) &
@@ -177,14 +180,18 @@ static uint32_t sifive_plic_claim(SiFivePLICState *plic,
uint32_t addrid)
int irq = (i << 5) + j;
uint32_t prio = plic->source_priority[irq];
int enabled = pending_enabled_not_claimed & (1 << j);
- if (enabled && prio > plic->target_priority[addrid]) {
- sifive_plic_set_pending(plic, irq, false);
- sifive_plic_set_claimed(plic, irq, true);
- return irq;
+ if (enabled && prio > max_prio) {
+ max_irq = irq;
+ max_prio = prio;
}
}
}
- return 0;
+
+ if (max_irq) {
+ sifive_plic_set_pending(plic, max_irq, false);
+ sifive_plic_set_claimed(plic, max_irq, true);
+ }
+ return max_irq;
}
static uint64_t sifive_plic_read(void *opaque, hwaddr addr, unsigned size)
--
2.27.0
- [PULL 00/63] riscv-to-apply queue, Alistair Francis, 2020/06/26
- [PULL 11/63] target/riscv: add vector amo operations, Alistair Francis, 2020/06/26
- [PULL 12/63] target/riscv: vector single-width integer add and subtract, Alistair Francis, 2020/06/26
- [PULL 13/63] target/riscv: vector widening integer add and subtract, Alistair Francis, 2020/06/26
- [PULL 01/63] riscv: plic: Honour source priorities,
Alistair Francis <=
- [PULL 02/63] riscv: plic: Add a couple of mising sifive_plic_update calls, Alistair Francis, 2020/06/26
- [PULL 04/63] target/riscv: implementation-defined constant parameters, Alistair Francis, 2020/06/26
- [PULL 15/63] target/riscv: vector bitwise logical instructions, Alistair Francis, 2020/06/26
- [PULL 05/63] target/riscv: support vector extension csr, Alistair Francis, 2020/06/26
- [PULL 16/63] target/riscv: vector single-width bit shift instructions, Alistair Francis, 2020/06/26
- [PULL 14/63] target/riscv: vector integer add-with-carry / subtract-with-borrow instructions, Alistair Francis, 2020/06/26
- [PULL 03/63] target/riscv: add vector extension field in CPURISCVState, Alistair Francis, 2020/06/26
- [PULL 19/63] target/riscv: vector integer min/max instructions, Alistair Francis, 2020/06/26