[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [PATCH v2 06/18] hw/block/nvme: Define trace events related to NS Ty
From: |
Alistair Francis |
Subject: |
Re: [PATCH v2 06/18] hw/block/nvme: Define trace events related to NS Types |
Date: |
Tue, 30 Jun 2020 13:18:21 -0700 |
On Wed, Jun 17, 2020 at 2:46 PM Dmitry Fomichev <dmitry.fomichev@wdc.com> wrote:
>
> A few trace events are defined that are relevant to implementing
> Namespace Types (NVMe TP 4056).
>
> Signed-off-by: Dmitry Fomichev <dmitry.fomichev@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> hw/block/trace-events | 11 +++++++++++
> 1 file changed, 11 insertions(+)
>
> diff --git a/hw/block/trace-events b/hw/block/trace-events
> index 423d491e27..3f3323fe38 100644
> --- a/hw/block/trace-events
> +++ b/hw/block/trace-events
> @@ -39,8 +39,13 @@ pci_nvme_create_cq(uint64_t addr, uint16_t cqid, uint16_t
> vector, uint16_t size,
> pci_nvme_del_sq(uint16_t qid) "deleting submission queue sqid=%"PRIu16""
> pci_nvme_del_cq(uint16_t cqid) "deleted completion queue, cqid=%"PRIu16""
> pci_nvme_identify_ctrl(void) "identify controller"
> +pci_nvme_identify_ctrl_csi(uint8_t csi) "identify controller, csi=0x%"PRIx8""
> pci_nvme_identify_ns(uint16_t ns) "identify namespace, nsid=%"PRIu16""
> +pci_nvme_identify_ns_csi(uint16_t ns, uint8_t csi) "identify namespace,
> nsid=%"PRIu16", csi=0x%"PRIx8""
> pci_nvme_identify_nslist(uint16_t ns) "identify namespace list,
> nsid=%"PRIu16""
> +pci_nvme_identify_nslist_csi(uint16_t ns, uint8_t csi) "identify namespace
> list, nsid=%"PRIu16", csi=0x%"PRIx8""
> +pci_nvme_list_ns_descriptors(void) "identify namespace descriptors"
> +pci_nvme_identify_cmd_set(void) "identify i/o command set"
> pci_nvme_getfeat_vwcache(const char* result) "get feature volatile write
> cache, result=%s"
> pci_nvme_getfeat_numq(int result) "get feature number of queues, result=%d"
> pci_nvme_setfeat_numq(int reqcq, int reqsq, int gotcq, int gotsq) "requested
> cq_count=%d sq_count=%d, responding with cq_count=%d sq_count=%d"
> @@ -59,6 +64,8 @@ pci_nvme_mmio_stopped(void) "cleared controller enable bit"
> pci_nvme_mmio_shutdown_set(void) "shutdown bit set"
> pci_nvme_mmio_shutdown_cleared(void) "shutdown bit cleared"
> pci_nvme_cmd_supp_and_effects_log_read(void) "commands supported and effects
> log read"
> +pci_nvme_css_nvm_cset_selected_by_host(uint32_t cc) "NVM command set
> selected by host, bar.cc=0x%"PRIx32""
> +pci_nvme_css_all_csets_sel_by_host(uint32_t cc) "all supported command sets
> selected by host, bar.cc=0x%"PRIx32""
>
> # nvme traces for error conditions
> pci_nvme_err_invalid_dma(void) "PRP/SGL is too small for transfer size"
> @@ -72,6 +79,9 @@ pci_nvme_err_invalid_admin_opc(uint8_t opc) "invalid admin
> opcode 0x%"PRIx8""
> pci_nvme_err_invalid_lba_range(uint64_t start, uint64_t len, uint64_t limit)
> "Invalid LBA start=%"PRIu64" len=%"PRIu64" limit=%"PRIu64""
> pci_nvme_err_invalid_effects_log_offset(uint64_t ofs) "commands supported
> and effects log offset must be 0, got %"PRIu64""
> pci_nvme_err_invalid_effects_log_len(uint32_t len) "commands supported and
> effects log size is 4096, got %"PRIu32""
> +pci_nvme_err_change_css_when_enabled(void) "changing CC.CSS while controller
> is enabled"
> +pci_nvme_err_only_nvm_cmd_set_avail(void) "setting 110b CC.CSS, but only NVM
> command set is enabled"
> +pci_nvme_err_invalid_iocsci(uint32_t idx) "unsupported command set
> combination index %"PRIu32""
> pci_nvme_err_invalid_del_sq(uint16_t qid) "invalid submission queue
> deletion, sid=%"PRIu16""
> pci_nvme_err_invalid_create_sq_cqid(uint16_t cqid) "failed creating
> submission queue, invalid cqid=%"PRIu16""
> pci_nvme_err_invalid_create_sq_sqid(uint16_t sqid) "failed creating
> submission queue, invalid sqid=%"PRIu16""
> @@ -127,6 +137,7 @@ pci_nvme_ub_db_wr_invalid_cqhead(uint32_t qid, uint16_t
> new_head) "completion qu
> pci_nvme_ub_db_wr_invalid_sq(uint32_t qid) "submission queue doorbell write
> for nonexistent queue, sqid=%"PRIu32", ignoring"
> pci_nvme_ub_db_wr_invalid_sqtail(uint32_t qid, uint16_t new_tail)
> "submission queue doorbell write value beyond queue size, sqid=%"PRIu32",
> new_head=%"PRIu16", ignoring"
> pci_nvme_unsupported_log_page(uint16_t lid) "unsupported log page
> 0x%"PRIx16""
> +pci_nvme_ub_unknown_css_value(void) "unknown value in cc.css field"
>
> # xen-block.c
> xen_block_realize(const char *type, uint32_t disk, uint32_t partition) "%s
> d%up%u"
> --
> 2.21.0
>
>
- Re: [PATCH v2 03/18] hw/block/nvme: Clean up unused AER definitions, (continued)
- [PATCH v2 06/18] hw/block/nvme: Define trace events related to NS Types, Dmitry Fomichev, 2020/06/17
- [PATCH v2 07/18] hw/block/nvme: Add support for Namespace Types, Dmitry Fomichev, 2020/06/17
- [PATCH v2 08/18] hw/block/nvme: Make Zoned NS Command Set definitions, Dmitry Fomichev, 2020/06/17
- [PATCH v2 09/18] hw/block/nvme: Define Zoned NS Command Set trace events, Dmitry Fomichev, 2020/06/17
- [PATCH v2 10/18] hw/block/nvme: Support Zoned Namespace Command Set, Dmitry Fomichev, 2020/06/17