Re: [PATCH v3 10/16] hw/riscv: microchip_pfsoc: Connect a DMA controller

[Alistair Francis]

On Mon, Aug 31, 2020 at 6:49 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> On the Icicle Kit board, the HSS firmware utilizes the on-chip DMA
> controller to move the 2nd stage bootloader in the system memory.
> Let's connect a DMA controller to Microchip PolarFire SoC.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

>
> ---
>
> (no changes since v2)
>
> Changes in v2:
> - connect 8 IRQs to the PLIC
>
>  include/hw/riscv/microchip_pfsoc.h | 11 +++++++++++
>  hw/riscv/microchip_pfsoc.c         | 15 +++++++++++++++
>  hw/riscv/Kconfig                   |  1 +
>  3 files changed, 27 insertions(+)
>
> diff --git a/include/hw/riscv/microchip_pfsoc.h 
> b/include/hw/riscv/microchip_pfsoc.h
> index d810ee8..63e7860 100644
> --- a/include/hw/riscv/microchip_pfsoc.h
> +++ b/include/hw/riscv/microchip_pfsoc.h
> @@ -23,6 +23,7 @@
>  #define HW_MICROCHIP_PFSOC_H
>
>  #include "hw/char/mchp_pfsoc_mmuart.h"
> +#include "hw/dma/sifive_pdma.h"
>  #include "hw/sd/cadence_sdhci.h"
>
>  typedef struct MicrochipPFSoCState {
> @@ -40,6 +41,7 @@ typedef struct MicrochipPFSoCState {
>      MchpPfSoCMMUartState *serial2;
>      MchpPfSoCMMUartState *serial3;
>      MchpPfSoCMMUartState *serial4;
> +    SiFivePDMAState dma;
>      CadenceSDHCIState sdhci;
>  } MicrochipPFSoCState;
>
> @@ -71,6 +73,7 @@ enum {
>      MICROCHIP_PFSOC_BUSERR_UNIT4,
>      MICROCHIP_PFSOC_CLINT,
>      MICROCHIP_PFSOC_L2CC,
> +    MICROCHIP_PFSOC_DMA,
>      MICROCHIP_PFSOC_L2LIM,
>      MICROCHIP_PFSOC_PLIC,
>      MICROCHIP_PFSOC_MMUART0,
> @@ -88,6 +91,14 @@ enum {
>  };
>
>  enum {
> +    MICROCHIP_PFSOC_DMA_IRQ0 = 5,
> +    MICROCHIP_PFSOC_DMA_IRQ1 = 6,
> +    MICROCHIP_PFSOC_DMA_IRQ2 = 7,
> +    MICROCHIP_PFSOC_DMA_IRQ3 = 8,
> +    MICROCHIP_PFSOC_DMA_IRQ4 = 9,
> +    MICROCHIP_PFSOC_DMA_IRQ5 = 10,
> +    MICROCHIP_PFSOC_DMA_IRQ6 = 11,
> +    MICROCHIP_PFSOC_DMA_IRQ7 = 12,
>      MICROCHIP_PFSOC_EMMC_SD_IRQ = 88,
>      MICROCHIP_PFSOC_MMUART0_IRQ = 90,
>      MICROCHIP_PFSOC_MMUART1_IRQ = 91,
> diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
> index 0b2e9ca..d8ec973 100644
> --- a/hw/riscv/microchip_pfsoc.c
> +++ b/hw/riscv/microchip_pfsoc.c
> @@ -13,6 +13,7 @@
>   * 2) eNVM (Embedded Non-Volatile Memory)
>   * 3) MMUARTs (Multi-Mode UART)
>   * 4) Cadence eMMC/SDHC controller and an SD card connected to it
> + * 5) SiFive Platform DMA (Direct Memory Access Controller)
>   *
>   * This board currently generates devicetree dynamically that indicates at 
> least
>   * two harts and up to five harts.
> @@ -71,6 +72,7 @@ static const struct MemmapEntry {
>      [MICROCHIP_PFSOC_BUSERR_UNIT4] =    {  0x1704000,     0x1000 },
>      [MICROCHIP_PFSOC_CLINT] =           {  0x2000000,    0x10000 },
>      [MICROCHIP_PFSOC_L2CC] =            {  0x2010000,     0x1000 },
> +    [MICROCHIP_PFSOC_DMA] =             {  0x3000000,   0x100000 },
>      [MICROCHIP_PFSOC_L2LIM] =           {  0x8000000,  0x2000000 },
>      [MICROCHIP_PFSOC_PLIC] =            {  0xc000000,  0x4000000 },
>      [MICROCHIP_PFSOC_MMUART0] =         { 0x20000000,     0x1000 },
> @@ -114,6 +116,9 @@ static void microchip_pfsoc_soc_instance_init(Object *obj)
>                           TYPE_RISCV_CPU_SIFIVE_U54);
>      qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", RESET_VECTOR);
>
> +    object_initialize_child(obj, "dma-controller", &s->dma,
> +                            TYPE_SIFIVE_PDMA);
> +
>      object_initialize_child(obj, "sd-controller", &s->sdhci,
>                              TYPE_CADENCE_SDHCI);
>  }
> @@ -218,6 +223,16 @@ static void microchip_pfsoc_soc_realize(DeviceState 
> *dev, Error **errp)
>          memmap[MICROCHIP_PFSOC_PLIC].size);
>      g_free(plic_hart_config);
>
> +    /* DMA */
> +    sysbus_realize(SYS_BUS_DEVICE(&s->dma), errp);
> +    sysbus_mmio_map(SYS_BUS_DEVICE(&s->dma), 0,
> +                    memmap[MICROCHIP_PFSOC_DMA].base);
> +    for (i = 0; i < SIFIVE_PDMA_IRQS; i++) {
> +        sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), i,
> +                           qdev_get_gpio_in(DEVICE(s->plic),
> +                                            MICROCHIP_PFSOC_DMA_IRQ0 + i));
> +    }
> +
>      /* SYSREG */
>      create_unimplemented_device("microchip.pfsoc.sysreg",
>          memmap[MICROCHIP_PFSOC_SYSREG].base,
> diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
> index 7412db9..9032cb0 100644
> --- a/hw/riscv/Kconfig
> +++ b/hw/riscv/Kconfig
> @@ -55,4 +55,5 @@ config MICROCHIP_PFSOC
>      select SIFIVE
>      select UNIMP
>      select MCHP_PFSOC_MMUART
> +    select SIFIVE_PDMA
>      select CADENCE_SDHCI
> --
> 2.7.4
>
>