[PATCH 1/1] accel/tcg: Fix computing is_write for mips

[Kele Huang]

Detect mips store instructions SWXC1 and SDXC1 for MIPS64 since
MIPS64r1, and MIPS32 since MIPS32r2.

Signed-off-by: Kele Huang <kele.hwang@gmail.com>
---
 accel/tcg/user-exec.c | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
index bb039eb32d..e69b4d8780 100644
--- a/accel/tcg/user-exec.c
+++ b/accel/tcg/user-exec.c
@@ -712,6 +712,27 @@ int cpu_signal_handler(int host_signum, void *pinfo,
 
     /* XXX: compute is_write */
     is_write = 0;
+
+    /*
+     * Detect store instructions. Required in all versions of MIPS64
+     * since MIPS64r1. Not available in MIPS32r1. Required by MIPS32r2
+     * and subsequent versions of MIPS32.
+     */
+    switch ((insn >> 3) & 0x7) {
+        case 0x1:
+            switch (insn & 0x7) {
+            case 0x0: /* SWXC1 */
+            case 0x1: /* SDXC1 */
+                is_write = 1;
+                break;
+            default:
+                break;
+            }
+            break;
+        default:
+            break;
+    }
+
     return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask);
 }
 
-- 
2.17.1