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[PULL 14/30] hw/arm: xlnx: Set all boards' GEM 'phy-addr' property value
From: |
Alistair Francis |
Subject: |
[PULL 14/30] hw/arm: xlnx: Set all boards' GEM 'phy-addr' property value to 23 |
Date: |
Thu, 10 Sep 2020 11:09:22 -0700 |
From: Bin Meng <bin.meng@windriver.com>
When cadence_gem model was created for Xilinx boards, the PHY address
was hard-coded to 23 in the GEM model. Now that we have introduced a
property we can use that to tell GEM model what our PHY address is.
Change all boards' GEM 'phy-addr' property value to 23, and set the
PHY address default value to 0 in the GEM model.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1598924352-89526-13-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/arm/xilinx_zynq.c | 1 +
hw/arm/xlnx-versal.c | 1 +
hw/arm/xlnx-zynqmp.c | 2 ++
hw/net/cadence_gem.c | 6 +++---
4 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
index 969ef0727c..9ffcc5606f 100644
--- a/hw/arm/xilinx_zynq.c
+++ b/hw/arm/xilinx_zynq.c
@@ -119,6 +119,7 @@ static void gem_init(NICInfo *nd, uint32_t base, qemu_irq
irq)
qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
qdev_set_nic_properties(dev, nd);
}
+ object_property_set_int(OBJECT(dev), "phy-addr", 23, &error_abort);
s = SYS_BUS_DEVICE(dev);
sysbus_realize_and_unref(s, &error_fatal);
sysbus_mmio_map(s, 0, base);
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
index e3aa4bd1e5..12ba6c4eba 100644
--- a/hw/arm/xlnx-versal.c
+++ b/hw/arm/xlnx-versal.c
@@ -165,6 +165,7 @@ static void versal_create_gems(Versal *s, qemu_irq *pic)
qemu_check_nic_model(nd, "cadence_gem");
qdev_set_nic_properties(dev, nd);
}
+ object_property_set_int(OBJECT(dev), "phy-addr", 23, &error_abort);
object_property_set_int(OBJECT(dev), "num-priority-queues", 2,
&error_abort);
object_property_set_link(OBJECT(dev), "dma", OBJECT(&s->mr_ps),
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
index c435b9d52a..7885bb1774 100644
--- a/hw/arm/xlnx-zynqmp.c
+++ b/hw/arm/xlnx-zynqmp.c
@@ -460,6 +460,8 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error
**errp)
}
object_property_set_int(OBJECT(&s->gem[i]), "revision", GEM_REVISION,
&error_abort);
+ object_property_set_int(OBJECT(&s->gem[i]), "phy-addr", 23,
+ &error_abort);
object_property_set_int(OBJECT(&s->gem[i]), "num-priority-queues", 2,
&error_abort);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->gem[i]), errp)) {
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index d80096bbe8..7a534691f1 100644
--- a/hw/net/cadence_gem.c
+++ b/hw/net/cadence_gem.c
@@ -250,7 +250,7 @@
#define GEM_PHYMNTNC_REG_SHIFT 18
/* Marvell PHY definitions */
-#define BOARD_PHY_ADDRESS 23 /* PHY address we will emulate a device at */
+#define BOARD_PHY_ADDRESS 0 /* PHY address we will emulate a device at */
#define PHY_REG_CONTROL 0
#define PHY_REG_STATUS 1
@@ -1446,7 +1446,7 @@ static uint64_t gem_read(void *opaque, hwaddr offset,
unsigned size)
uint32_t phy_addr, reg_num;
phy_addr = (retval & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT;
- if (phy_addr == s->phy_addr || phy_addr == 0) {
+ if (phy_addr == s->phy_addr) {
reg_num = (retval & GEM_PHYMNTNC_REG) >>
GEM_PHYMNTNC_REG_SHIFT;
retval &= 0xFFFF0000;
retval |= gem_phy_read(s, reg_num);
@@ -1569,7 +1569,7 @@ static void gem_write(void *opaque, hwaddr offset,
uint64_t val,
uint32_t phy_addr, reg_num;
phy_addr = (val & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT;
- if (phy_addr == s->phy_addr || phy_addr == 0) {
+ if (phy_addr == s->phy_addr) {
reg_num = (val & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT;
gem_phy_write(s, reg_num, val);
}
--
2.28.0
- [PULL 05/30] target/riscv: cpu: Set reset vector based on the configured property value, (continued)
- [PULL 05/30] target/riscv: cpu: Set reset vector based on the configured property value, Alistair Francis, 2020/09/10
- [PULL 04/30] hw/riscv: hart: Add a new 'resetvec' property, Alistair Francis, 2020/09/10
- [PULL 07/30] hw/char: Add Microchip PolarFire SoC MMUART emulation, Alistair Francis, 2020/09/10
- [PULL 08/30] hw/riscv: microchip_pfsoc: Connect 5 MMUARTs, Alistair Francis, 2020/09/10
- [PULL 09/30] hw/sd: Add Cadence SDHCI emulation, Alistair Francis, 2020/09/10
- [PULL 06/30] hw/riscv: Initial support for Microchip PolarFire SoC Icicle Kit board, Alistair Francis, 2020/09/10
- [PULL 11/30] hw/dma: Add SiFive platform DMA controller emulation, Alistair Francis, 2020/09/10
- [PULL 10/30] hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI controller and an SD card, Alistair Francis, 2020/09/10
- [PULL 12/30] hw/riscv: microchip_pfsoc: Connect a DMA controller, Alistair Francis, 2020/09/10
- [PULL 13/30] hw/net: cadence_gem: Add a new 'phy-addr' property, Alistair Francis, 2020/09/10
- [PULL 14/30] hw/arm: xlnx: Set all boards' GEM 'phy-addr' property value to 23,
Alistair Francis <=
- [PULL 15/30] hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMs, Alistair Francis, 2020/09/10
- [PULL 16/30] hw/riscv: microchip_pfsoc: Hook GPIO controllers, Alistair Francis, 2020/09/10
- [PULL 18/30] hw/riscv: sifive_u: Connect a DMA controller, Alistair Francis, 2020/09/10
- [PULL 17/30] hw/riscv: clint: Avoid using hard-coded timebase frequency, Alistair Francis, 2020/09/10
- [PULL 19/30] hw/riscv: Move sifive_e_prci model to hw/misc, Alistair Francis, 2020/09/10
- [PULL 20/30] hw/riscv: Move sifive_u_prci model to hw/misc, Alistair Francis, 2020/09/10
- [PULL 21/30] hw/riscv: Move sifive_u_otp model to hw/misc, Alistair Francis, 2020/09/10
- [PULL 22/30] hw/riscv: Move sifive_gpio model to hw/gpio, Alistair Francis, 2020/09/10
- [PULL 25/30] hw/riscv: Move riscv_htif model to hw/char, Alistair Francis, 2020/09/10
- [PULL 23/30] hw/riscv: Move sifive_clint model to hw/intc, Alistair Francis, 2020/09/10