Re: [PATCH 1/2] arm.risu: Correct VLDR/VSTR U=0 patterns

[Alex Bennée]

Peter Maydell <peter.maydell@linaro.org> writes:

> Correct the VLDR and VSTR patterns, which claimed to be setting U=0
> but in fact left it identical to the U=1 pattern due to a
> cut-and-paste error.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> Somehow the pre-generated test binaries I have from Alex have
> U=0 insns in them -- I suspect this got fixed locally but never
> made it upstream ?

Hmm my current set of aarch32 test patterns have U=1 throughout. So if
it did get fixed locally it also got lost.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>

-- 
Alex Bennée