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Re: [PATCH 00/14] raspi: add the bcm2835 cprman clock manager


From: Philippe Mathieu-Daudé
Subject: Re: [PATCH 00/14] raspi: add the bcm2835 cprman clock manager
Date: Fri, 25 Sep 2020 14:55:47 +0200
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.11.0

Cc'ing Paul/Niek/Havard.

On 9/25/20 12:17 PM, Luc Michel wrote:
> Hi,
> 
> This series add the BCM2835 cprman clock manager peripheral to the
> Raspberry Pi machine.
> 
> Patches 1-3 are preliminary changes, patches 4-12 are the actual
> implementation.
> 
> The two last patches add a clock input to the PL011 and
> connect it to the cprman and are RFC.
> 
> This series has been tested with Linux 5.4.61 (the current raspios
> version). It fixes the kernel Oops at boot time due to invalid UART
> clock value, and other warnings/errors here and there because of bad
> clocks or lack of cprman.
> 
> Here is the clock tree as seen by Linux when booted in QEMU:
> (/sys/kernel/debug/clk/clk_summary with some columns removed)
> 
>                         enable  prepare              
>    clock                 count    count          rate
> -----------------------------------------------------
>  otg                         0        0     480000000
>  osc                         5        5      19200000
>     gp2                      1        1         32768
>     tsens                    0        0       1920000
>     otp                      0        0       4800000
>     timer                    0        0       1000002
>     pllh                     4        4     864000000
>        pllh_pix_prediv       1        1       3375000
>           pllh_pix           0        0        337500
>        pllh_aux              1        1     216000000
>           vec                0        0     108000000
>        pllh_rcal_prediv      1        1       3375000
>           pllh_rcal          0        0        337500
>     plld                     3        3    2000000024
>        plld_dsi1             0        0       7812501
>        plld_dsi0             0        0       7812501
>        plld_per              3        3     500000006
>           gp1                1        1      25000000
>           uart               1        2      47999625
>        plld_core             2        2     500000006
>           sdram              0        0     166666668
>     pllc                     3        3    2400000000
>        pllc_per              1        1    1200000000
>           emmc               0        0     200000000
>        pllc_core2            0        0       9375000
>        pllc_core1            0        0       9375000
>        pllc_core0            2        2    1200000000
>           vpu                1        1     700000000
>              aux_spi2        0        0     700000000
>              aux_spi1        0        0     700000000
>              aux_uart        0        0     700000000
>              peri_image      0        0     700000000
>     plla                     2        2    2250000000
>        plla_ccp2             0        0       8789063
>        plla_dsi0             0        0       8789063
>        plla_core             1        1     750000000
>           h264               0        0     250000000
>           isp                0        0     250000000
>  dsi1p                       0        0             0
>  dsi0p                       0        0             0
>  dsi1e                       0        0             0
>  dsi0e                       0        0             0
>  cam1                        0        0             0
>  cam0                        0        0             0
>  dpi                         0        0             0
>  tec                         0        0             0
>  smi                         0        0             0
>  slim                        0        0             0
>  gp0                         0        0             0
>  dft                         0        0             0
>  aveo                        0        0             0
>  pcm                         0        0             0
>  pwm                         0        0             0
>  hsm                         0        0             0
> 
> It shows small differences with real hardware due other missing
> peripherals for which the driver turn the clock off (like tsens).
> 
> Luc Michel (14):
>   hw/core/clock: provide the VMSTATE_ARRAY_CLOCK macro
>   hw/core/clock: trace clock values in Hz instead of ns
>   hw/arm/raspi: fix cprman base address
>   hw/arm/raspi: add a skeleton implementation of the cprman
>   hw/misc/bcm2835_cprman: add a PLL skeleton implementation
>   hw/misc/bcm2835_cprman: implement PLLs behaviour
>   hw/misc/bcm2835_cprman: add a PLL channel skeleton implementation
>   hw/misc/bcm2835_cprman: implement PLL channels behaviour
>   hw/misc/bcm2835_cprman: add a clock mux skeleton implementation
>   hw/misc/bcm2835_cprman: implement clock mux behaviour
>   hw/misc/bcm2835_cprman: add the DSI0HSCK multiplexer
>   hw/misc/bcm2835_cprman: add sane reset values to the registers
>   hw/char/pl011: add a clock input
>   hw/arm/bcm2835_peripherals: connect the UART clock
> 

>  14 files changed, 2118 insertions(+), 12 deletions(-)
ouch... o_O huge device...

Tested on top of my raspi branch with raspi[0123]:
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>



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