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[RFC v5 33/68] target/riscv: rvv-1.0: allow load element with sign-exten
From: |
frank . chang |
Subject: |
[RFC v5 33/68] target/riscv: rvv-1.0: allow load element with sign-extended |
Date: |
Wed, 30 Sep 2020 03:04:08 +0800 |
From: Frank Chang <frank.chang@sifive.com>
For some vector instructions (e.g. vmv.s.x), the element is loaded with
sign-extended.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/insn_trans/trans_rvv.c.inc | 32 +++++++++++++++++--------
1 file changed, 22 insertions(+), 10 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index ae2b224b0f..6c542a97d8 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -3068,17 +3068,29 @@ static bool trans_vid_v(DisasContext *s, arg_vid_v *a)
/* Integer Extract Instruction */
static void load_element(TCGv_i64 dest, TCGv_ptr base,
- int ofs, int sew)
+ int ofs, int sew, bool sign)
{
switch (sew) {
case MO_8:
- tcg_gen_ld8u_i64(dest, base, ofs);
+ if (!sign) {
+ tcg_gen_ld8u_i64(dest, base, ofs);
+ } else {
+ tcg_gen_ld8s_i64(dest, base, ofs);
+ }
break;
case MO_16:
- tcg_gen_ld16u_i64(dest, base, ofs);
+ if (!sign) {
+ tcg_gen_ld16u_i64(dest, base, ofs);
+ } else {
+ tcg_gen_ld16s_i64(dest, base, ofs);
+ }
break;
case MO_32:
- tcg_gen_ld32u_i64(dest, base, ofs);
+ if (!sign) {
+ tcg_gen_ld32u_i64(dest, base, ofs);
+ } else {
+ tcg_gen_ld32s_i64(dest, base, ofs);
+ }
break;
case MO_64:
tcg_gen_ld_i64(dest, base, ofs);
@@ -3133,7 +3145,7 @@ static void vec_element_loadx(DisasContext *s, TCGv_i64
dest,
/* Perform the load. */
load_element(dest, base,
- vreg_ofs(s, vreg), s->sew);
+ vreg_ofs(s, vreg), s->sew, false);
tcg_temp_free_ptr(base);
tcg_temp_free_i32(ofs);
@@ -3151,9 +3163,9 @@ static void vec_element_loadx(DisasContext *s, TCGv_i64
dest,
}
static void vec_element_loadi(DisasContext *s, TCGv_i64 dest,
- int vreg, int idx)
+ int vreg, int idx, bool sign)
{
- load_element(dest, cpu_env, endian_ofs(s, vreg, idx), s->sew);
+ load_element(dest, cpu_env, endian_ofs(s, vreg, idx), s->sew, sign);
}
static bool trans_vext_x_v(DisasContext *s, arg_r *a)
@@ -3163,7 +3175,7 @@ static bool trans_vext_x_v(DisasContext *s, arg_r *a)
if (a->rs1 == 0) {
/* Special case vmv.x.s rd, vs2. */
- vec_element_loadi(s, tmp, a->rs2, 0);
+ vec_element_loadi(s, tmp, a->rs2, 0, false);
} else {
/* This instruction ignores LMUL and vector register groups */
int vlmax = s->vlen >> (3 + s->sew);
@@ -3245,7 +3257,7 @@ static bool trans_vfmv_f_s(DisasContext *s, arg_vfmv_f_s
*a)
(s->mstatus_fs != 0) && (s->sew != 0)) {
unsigned int len = 8 << s->sew;
- vec_element_loadi(s, cpu_fpr[a->rd], a->rs2, 0);
+ vec_element_loadi(s, cpu_fpr[a->rd], a->rs2, 0, false);
if (len < 64) {
tcg_gen_ori_i64(cpu_fpr[a->rd], cpu_fpr[a->rd],
MAKE_64BIT_MASK(len, 64 - len));
@@ -3347,7 +3359,7 @@ static bool trans_vrgather_vx(DisasContext *s, arg_rmrr
*a)
TCGv_i64 dest = tcg_temp_new_i64();
if (a->rs1 == 0) {
- vec_element_loadi(s, dest, a->rs2, 0);
+ vec_element_loadi(s, dest, a->rs2, 0, false);
} else {
vec_element_loadx(s, dest, a->rs2, cpu_gpr[a->rs1], vlmax);
}
--
2.17.1
- [RFC v5 23/68] target/riscv: rvv-1.0: load/store whole register instructions, (continued)
- [RFC v5 23/68] target/riscv: rvv-1.0: load/store whole register instructions, frank . chang, 2020/09/29
- [RFC v5 24/68] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns, frank . chang, 2020/09/29
- [RFC v5 25/68] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation, frank . chang, 2020/09/29
- [RFC v5 26/68] target/riscv: rvv-1.0: floating-point square-root instruction, frank . chang, 2020/09/29
- [RFC v5 27/68] target/riscv: rvv-1.0: floating-point classify instructions, frank . chang, 2020/09/29
- [RFC v5 28/68] target/riscv: rvv-1.0: mask population count instruction, frank . chang, 2020/09/29
- [RFC v5 29/68] target/riscv: rvv-1.0: find-first-set mask bit instruction, frank . chang, 2020/09/29
- [RFC v5 30/68] target/riscv: rvv-1.0: set-X-first mask bit instructions, frank . chang, 2020/09/29
- [RFC v5 31/68] target/riscv: rvv-1.0: iota instruction, frank . chang, 2020/09/29
- [RFC v5 32/68] target/riscv: rvv-1.0: element index instruction, frank . chang, 2020/09/29
- [RFC v5 33/68] target/riscv: rvv-1.0: allow load element with sign-extended,
frank . chang <=
- [RFC v5 34/68] target/riscv: rvv-1.0: register gather instructions, frank . chang, 2020/09/29
- [RFC v5 35/68] target/riscv: rvv-1.0: integer scalar move instructions, frank . chang, 2020/09/29
- [RFC v5 36/68] target/riscv: rvv-1.0: floating-point move instruction, frank . chang, 2020/09/29
- [RFC v5 37/68] target/riscv: rvv-1.0: floating-point scalar move instructions, frank . chang, 2020/09/29
- [RFC v5 38/68] target/riscv: rvv-1.0: whole register move instructions, frank . chang, 2020/09/29
- [RFC v5 40/68] target/riscv: rvv-1.0: single-width averaging add and subtract instructions, frank . chang, 2020/09/29
- [RFC v5 41/68] target/riscv: rvv-1.0: single-width bit shift instructions, frank . chang, 2020/09/29
- [RFC v5 39/68] target/riscv: rvv-1.0: integer extension instructions, frank . chang, 2020/09/29
- [RFC v5 42/68] target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow, frank . chang, 2020/09/29
- [RFC v5 43/68] target/riscv: rvv-1.0: narrowing integer right shift instructions, frank . chang, 2020/09/29