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[RFC v5 56/68] target/riscv: rvv-1.0: remove vmford.vv and vmford.vf
From: |
frank . chang |
Subject: |
[RFC v5 56/68] target/riscv: rvv-1.0: remove vmford.vv and vmford.vf |
Date: |
Wed, 30 Sep 2020 03:04:31 +0800 |
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/helper.h | 6 ------
target/riscv/insn32.decode | 2 --
target/riscv/insn_trans/trans_rvv.c.inc | 2 --
target/riscv/vector_helper.c | 7 -------
4 files changed, 17 deletions(-)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 24d575162d..cdaf427060 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -952,12 +952,6 @@ DEF_HELPER_6(vmfgt_vf_d, void, ptr, ptr, i64, ptr, env,
i32)
DEF_HELPER_6(vmfge_vf_h, void, ptr, ptr, i64, ptr, env, i32)
DEF_HELPER_6(vmfge_vf_w, void, ptr, ptr, i64, ptr, env, i32)
DEF_HELPER_6(vmfge_vf_d, void, ptr, ptr, i64, ptr, env, i32)
-DEF_HELPER_6(vmford_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
-DEF_HELPER_6(vmford_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
-DEF_HELPER_6(vmford_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
-DEF_HELPER_6(vmford_vf_h, void, ptr, ptr, i64, ptr, env, i32)
-DEF_HELPER_6(vmford_vf_w, void, ptr, ptr, i64, ptr, env, i32)
-DEF_HELPER_6(vmford_vf_d, void, ptr, ptr, i64, ptr, env, i32)
DEF_HELPER_5(vfclass_v_h, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vfclass_v_w, void, ptr, ptr, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index d6468750a1..db84c0d1c9 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -557,8 +557,6 @@ vmfle_vv 011001 . ..... ..... 001 ..... 1010111 @r_vm
vmfle_vf 011001 . ..... ..... 101 ..... 1010111 @r_vm
vmfgt_vf 011101 . ..... ..... 101 ..... 1010111 @r_vm
vmfge_vf 011111 . ..... ..... 101 ..... 1010111 @r_vm
-vmford_vv 011010 . ..... ..... 001 ..... 1010111 @r_vm
-vmford_vf 011010 . ..... ..... 101 ..... 1010111 @r_vm
vfclass_v 010011 . ..... 10000 001 ..... 1010111 @r2_vm
vfmerge_vfm 010111 0 ..... ..... 101 ..... 1010111 @r_vm_0
vfmv_v_f 010111 1 00000 ..... 101 ..... 1010111 @r2
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index 20781ab5d1..9225780145 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -2673,7 +2673,6 @@ GEN_OPFVV_TRANS(vmfeq_vv, opfvv_cmp_check)
GEN_OPFVV_TRANS(vmfne_vv, opfvv_cmp_check)
GEN_OPFVV_TRANS(vmflt_vv, opfvv_cmp_check)
GEN_OPFVV_TRANS(vmfle_vv, opfvv_cmp_check)
-GEN_OPFVV_TRANS(vmford_vv, opfvv_cmp_check)
static bool opfvf_cmp_check(DisasContext *s, arg_rmrr *a)
{
@@ -2689,7 +2688,6 @@ GEN_OPFVF_TRANS(vmflt_vf, opfvf_cmp_check)
GEN_OPFVF_TRANS(vmfle_vf, opfvf_cmp_check)
GEN_OPFVF_TRANS(vmfgt_vf, opfvf_cmp_check)
GEN_OPFVF_TRANS(vmfge_vf, opfvf_cmp_check)
-GEN_OPFVF_TRANS(vmford_vf, opfvf_cmp_check)
/* Vector Floating-Point Classify Instruction */
GEN_OPFV_TRANS(vfclass_v, opfv_check)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 549a476490..c5e6572012 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -3839,13 +3839,6 @@ GEN_VEXT_CMP_VF(vmfge_vf_h, uint16_t, H2, vmfge16)
GEN_VEXT_CMP_VF(vmfge_vf_w, uint32_t, H4, vmfge32)
GEN_VEXT_CMP_VF(vmfge_vf_d, uint64_t, H8, vmfge64)
-GEN_VEXT_CMP_VV_ENV(vmford_vv_h, uint16_t, H2, !float16_unordered_quiet)
-GEN_VEXT_CMP_VV_ENV(vmford_vv_w, uint32_t, H4, !float32_unordered_quiet)
-GEN_VEXT_CMP_VV_ENV(vmford_vv_d, uint64_t, H8, !float64_unordered_quiet)
-GEN_VEXT_CMP_VF(vmford_vf_h, uint16_t, H2, !float16_unordered_quiet)
-GEN_VEXT_CMP_VF(vmford_vf_w, uint32_t, H4, !float32_unordered_quiet)
-GEN_VEXT_CMP_VF(vmford_vf_d, uint64_t, H8, !float64_unordered_quiet)
-
/* Vector Floating-Point Classify Instruction */
#define OPIVV1(NAME, TD, T2, TX2, HD, HS2, OP) \
static void do_##NAME(void *vd, void *vs2, int i) \
--
2.17.1
- [RFC v5 46/68] target/riscv: rvv-1.0: integer comparison instructions, (continued)
- [RFC v5 46/68] target/riscv: rvv-1.0: integer comparison instructions, frank . chang, 2020/09/29
- [RFC v5 47/68] target/riscv: rvv-1.0: floating-point compare instructions, frank . chang, 2020/09/29
- [RFC v5 48/68] target/riscv: rvv-1.0: mask-register logical instructions, frank . chang, 2020/09/29
- [RFC v5 49/68] target/riscv: rvv-1.0: slide instructions, frank . chang, 2020/09/29
- [RFC v5 51/68] target/riscv: rvv-1.0: narrowing fixed-point clip instructions, frank . chang, 2020/09/29
- [RFC v5 50/68] target/riscv: rvv-1.0: floating-point slide instructions, frank . chang, 2020/09/29
- [RFC v5 52/68] target/riscv: rvv-1.0: single-width floating-point reduction, frank . chang, 2020/09/29
- [RFC v5 53/68] target/riscv: rvv-1.0: widening floating-point reduction instructions, frank . chang, 2020/09/29
- [RFC v5 54/68] target/riscv: rvv-1.0: single-width scaling shift instructions, frank . chang, 2020/09/29
- [RFC v5 55/68] target/riscv: rvv-1.0: remove widening saturating scaled multiply-add, frank . chang, 2020/09/29
- [RFC v5 56/68] target/riscv: rvv-1.0: remove vmford.vv and vmford.vf,
frank . chang <=
- [RFC v5 57/68] target/riscv: rvv-1.0: remove integer extract instruction, frank . chang, 2020/09/29
- [RFC v5 58/68] target/riscv: rvv-1.0: floating-point min/max instructions, frank . chang, 2020/09/29
- [RFC v5 59/68] target/riscv: introduce floating-point rounding mode enum, frank . chang, 2020/09/29
- [RFC v5 60/68] target/riscv: rvv-1.0: floating-point/integer type-convert instructions, frank . chang, 2020/09/29
- [RFC v5 61/68] target/riscv: rvv-1.0: widening floating-point/integer type-convert, frank . chang, 2020/09/29
- [RFC v5 62/68] target/riscv: add "set round to odd" rounding mode helper function, frank . chang, 2020/09/29
- [RFC v5 63/68] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert, frank . chang, 2020/09/29
- [RFC v5 64/68] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits, frank . chang, 2020/09/29
- [RFC v5 65/68] target/riscv: gdb: modify gdb csr xml file to align with csr register map, frank . chang, 2020/09/29
- [RFC v5 66/68] target/riscv: gdb: support vector registers for rv64 & rv32, frank . chang, 2020/09/29