Re: [PATCH] target/mips: Allow executing MSA instructions on Loongson-3A4000

[chen huacai]

Reviewed-by: Huacai Chen <chenhc@lemote.com>

On Tue, Dec 1, 2020 at 2:24 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 11/30/20 4:22 AM, Philippe Mathieu-Daudé wrote:
> > The Loongson-3A4000 is a GS464V-based processor with MIPS MSA ASE:
> > https://www.mail-archive.com/qemu-devel@nongnu.org/msg763059.html
> >
> > Commit af868995e1b correctly set the 'MSA present' bit of Config3
> > register, but forgot to allow the MSA instructions decoding in
> > insn_flags, so executing them triggers a 'Reserved Instruction'.
> >
> > Fix by adding the ASE_MSA mask to insn_flags.
> >
> > Fixes: af868995e1b ("target/mips: Add Loongson-3 CPU definition")
> > Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> > ---
> > Buggy since 5.1, so probably not a big deal.
> > ---
> >  target/mips/translate_init.c.inc | 4 ++--
> >  1 file changed, 2 insertions(+), 2 deletions(-)
>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
>
> r~
>


-- 
Huacai Chen