Re: [PATCH-for 5.2?] hw/core/ressetable: fix reset count decrement

[Philippe Mathieu-Daudé]

On 12/2/20 5:40 PM, Damien Hedde wrote:
> The reset count was only decremented if the device was in a single
> reset.
> 
> Also move the decrement before calling the exit phase method to fix
> problem of reset state evaluation during that call. Update the doc
> accordingly.
> 
> Signed-off-by: Damien Hedde <damien.hedde@greensocs.com>
> Fixes: 1905297 ("Zynq7000 UART clock reset initialization", 2020-11-23)

$ git show 1905297
fatal: ambiguous argument '1905297': unknown revision or path not in the
working tree.

Beside, typo ressetable -> resettable in subject.

> Reported-by: Michael Peter <michael.peter@hensoldt-cyber.com>
> --
> 
> Hi all,
> 
> While looking at the bug reported by Michael and his patch. I found another
> bug. Apparently I forgot to decrement the reset count if there was several
> reset at the same time.
> 
> This patch fixes that.
> 
> I also moved the place of the decrement: before calling the exit phase method.
> it globally fixes Michael's reported bug, as I think it will avoid some boiler
> plate code in every exit phase method we do.
> 
> Only other place where the reset state is checked is in the
> hw/char/cadence-uart.c so it does not have high impact.
> 
> I'm not sure if this meets the condition for 5.2 as it changes a documented
> feature. In that case we can just accept Michael solution and I'll fix the
> rest later.
> 
> Here's the pointer for the bug and michael's patch.
> https://lists.nongnu.org/archive/html/qemu-devel/2020-11/msg05786.html
> https://lists.nongnu.org/archive/html/qemu-devel/2020-11/msg06105.html
> 
> Damien