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Re: [PATCH] xive: Add more trace events
From: |
David Gibson |
Subject: |
Re: [PATCH] xive: Add more trace events |
Date: |
Thu, 3 Dec 2020 13:40:13 +1100 |
On Fri, Nov 27, 2020 at 02:36:54PM +0100, Cédric Le Goater wrote:
> These are useful to understand IRQ requests from the OS.
>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
>
> David, Feel free to merge with the previous.
Done, thanks.
>
> hw/intc/spapr_xive.c | 6 ++++++
> hw/intc/spapr_xive_kvm.c | 5 +++++
> hw/intc/trace-events | 7 +++++++
> 3 files changed, 18 insertions(+)
>
> diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c
> index 644cc85cbdc9..db6d0e7a3a12 100644
> --- a/hw/intc/spapr_xive.c
> +++ b/hw/intc/spapr_xive.c
> @@ -563,6 +563,8 @@ static int spapr_xive_claim_irq(SpaprInterruptController
> *intc, int lisn,
>
> assert(lisn < xive->nr_irqs);
>
> + trace_spapr_xive_claim_irq(lisn, lsi);
> +
> if (xive_eas_is_valid(&xive->eat[lisn])) {
> error_setg(errp, "IRQ %d is not free", lisn);
> return -EBUSY;
> @@ -588,6 +590,8 @@ static void spapr_xive_free_irq(SpaprInterruptController
> *intc, int lisn)
> SpaprXive *xive = SPAPR_XIVE(intc);
> assert(lisn < xive->nr_irqs);
>
> + trace_spapr_xive_free_irq(lisn);
> +
> xive->eat[lisn].w &= cpu_to_be64(~EAS_VALID);
> }
>
> @@ -654,6 +658,8 @@ static void spapr_xive_set_irq(SpaprInterruptController
> *intc, int irq, int val)
> {
> SpaprXive *xive = SPAPR_XIVE(intc);
>
> + trace_spapr_xive_set_irq(irq, val);
> +
> if (spapr_xive_in_kernel(xive)) {
> kvmppc_xive_source_set_irq(&xive->source, irq, val);
> } else {
> diff --git a/hw/intc/spapr_xive_kvm.c b/hw/intc/spapr_xive_kvm.c
> index e8667ce5f621..acc8c3650c4c 100644
> --- a/hw/intc/spapr_xive_kvm.c
> +++ b/hw/intc/spapr_xive_kvm.c
> @@ -20,6 +20,7 @@
> #include "hw/ppc/spapr_xive.h"
> #include "hw/ppc/xive.h"
> #include "kvm_ppc.h"
> +#include "trace.h"
>
> #include <sys/ioctl.h>
>
> @@ -163,6 +164,8 @@ int kvmppc_xive_cpu_connect(XiveTCTX *tctx, Error **errp)
>
> vcpu_id = kvm_arch_vcpu_id(tctx->cs);
>
> + trace_kvm_xive_cpu_connect(vcpu_id);
> +
> ret = kvm_vcpu_enable_cap(tctx->cs, KVM_CAP_PPC_IRQ_XIVE, 0, xive->fd,
> vcpu_id, 0);
> if (ret < 0) {
> @@ -308,6 +311,8 @@ uint64_t kvmppc_xive_esb_rw(XiveSource *xsrc, int srcno,
> uint32_t offset,
> return xive_esb_rw(xsrc, srcno, offset, data, 1);
> }
>
> + trace_kvm_xive_source_reset(srcno);
> +
> /*
> * Special Load EOI handling for LSI sources. Q bit is never set
> * and the interrupt should be re-triggered if the level is still
> diff --git a/hw/intc/trace-events b/hw/intc/trace-events
> index 77addc100f72..8ed397a0d587 100644
> --- a/hw/intc/trace-events
> +++ b/hw/intc/trace-events
> @@ -205,6 +205,9 @@ bcm2835_ic_set_gpu_irq(int irq, int level) "GPU irq #%d
> level %d"
> bcm2835_ic_set_cpu_irq(int irq, int level) "CPU irq #%d level %d"
>
> # spapr_xive.c
> +spapr_xive_claim_irq(uint32_t lisn, bool lsi) "lisn=0x%x lsi=%d"
> +spapr_xive_free_irq(uint32_t lisn) "lisn=0x%x"
> +spapr_xive_set_irq(uint32_t lisn, uint32_t val) "lisn=0x%x val=%d"
> spapr_xive_get_source_info(uint64_t flags, uint64_t lisn) "flags=0x%"PRIx64"
> lisn=0x%"PRIx64
> spapr_xive_set_source_config(uint64_t flags, uint64_t lisn, uint64_t target,
> uint64_t priority, uint64_t eisn) "flags=0x%"PRIx64" lisn=0x%"PRIx64"
> target=0x%"PRIx64" priority=0x%"PRIx64" eisn=0x%"PRIx64
> spapr_xive_get_source_config(uint64_t flags, uint64_t lisn)
> "flags=0x%"PRIx64" lisn=0x%"PRIx64
> @@ -217,6 +220,10 @@ spapr_xive_esb(uint64_t flags, uint64_t lisn, uint64_t
> offset, uint64_t data) "f
> spapr_xive_sync(uint64_t flags, uint64_t lisn) "flags=0x%"PRIx64"
> lisn=0x%"PRIx64
> spapr_xive_reset(uint64_t flags) "flags=0x%"PRIx64
>
> +# spapr_xive_kvm.c
> +kvm_xive_cpu_connect(uint32_t id) "connect CPU%d to KVM device"
> +kvm_xive_source_reset(uint32_t srcno) "IRQ 0x%x"
> +
> # xive.c
> xive_tctx_accept(uint32_t index, uint8_t ring, uint8_t ipb, uint8_t pipr,
> uint8_t cppr, uint8_t nsr) "target=%d ring=0x%x IBP=0x%02x PIPR=0x%02x
> CPPR=0x%02x NSR=0x%02x ACK"
> xive_tctx_notify(uint32_t index, uint8_t ring, uint8_t ipb, uint8_t pipr,
> uint8_t cppr, uint8_t nsr) "target=%d ring=0x%x IBP=0x%02x PIPR=0x%02x
> CPPR=0x%02x NSR=0x%02x raise !"
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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