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[PATCH 5/5] hw/mips/boston: Make use of bootloader helper
From: |
Jiaxun Yang |
Subject: |
[PATCH 5/5] hw/mips/boston: Make use of bootloader helper |
Date: |
Mon, 7 Dec 2020 13:14:09 +0800 |
Use bootloader helper to generate CM Base setting code
and kernel jump.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
hw/mips/boston.c | 60 +++++++++++-------------------------------------
1 file changed, 13 insertions(+), 47 deletions(-)
diff --git a/hw/mips/boston.c b/hw/mips/boston.c
index 3d40867dc4..c784f8ee62 100644
--- a/hw/mips/boston.c
+++ b/hw/mips/boston.c
@@ -281,40 +281,20 @@ static void gen_firmware(uint32_t *p, hwaddr
kernel_entry, hwaddr fdt_addr,
const uint32_t gic_base = 0x16120000;
const uint32_t cpc_base = 0x16200000;
- /* Move CM GCRs */
if (is_64b) {
- stl_p(p++, 0x40287803); /* dmfc0 $8, CMGCRBase */
- stl_p(p++, 0x00084138); /* dsll $8, $8, 4 */
+ bl_gen_writeq(&p, cm_base,
+ cpu_mips_phys_to_kseg1(NULL, GCR_BASE_ADDR +
GCR_BASE_OFS));
+ bl_gen_writeq(&p, gic_base | GCR_GIC_BASE_GICEN_MSK,
+ cpu_mips_phys_to_kseg1(NULL, cm_base + GCR_GIC_BASE_OFS));
+ bl_gen_writeq(&p, cpc_base | GCR_CPC_BASE_CPCEN_MSK,
+ cpu_mips_phys_to_kseg1(NULL, cm_base + GCR_CPC_BASE_OFS));
} else {
- stl_p(p++, 0x40087803); /* mfc0 $8, CMGCRBase */
- stl_p(p++, 0x00084100); /* sll $8, $8, 4 */
- }
- stl_p(p++, 0x3c09a000); /* lui $9, 0xa000 */
- stl_p(p++, 0x01094025); /* or $8, $9 */
- stl_p(p++, 0x3c0a0000 | (cm_base >> 16)); /* lui $10, cm_base >> 16 */
- if (is_64b) {
- stl_p(p++, 0xfd0a0008); /* sd $10, 0x8($8) */
- } else {
- stl_p(p++, 0xad0a0008); /* sw $10, 0x8($8) */
- }
- stl_p(p++, 0x012a4025); /* or $8, $10 */
-
- /* Move & enable GIC GCRs */
- stl_p(p++, 0x3c090000 | (gic_base >> 16)); /* lui $9, gic_base >> 16 */
- stl_p(p++, 0x35290001); /* ori $9, 0x1 */
- if (is_64b) {
- stl_p(p++, 0xfd090080); /* sd $9, 0x80($8) */
- } else {
- stl_p(p++, 0xad090080); /* sw $9, 0x80($8) */
- }
-
- /* Move & enable CPC GCRs */
- stl_p(p++, 0x3c090000 | (cpc_base >> 16)); /* lui $9, cpc_base >> 16 */
- stl_p(p++, 0x35290001); /* ori $9, 0x1 */
- if (is_64b) {
- stl_p(p++, 0xfd090088); /* sd $9, 0x88($8) */
- } else {
- stl_p(p++, 0xad090088); /* sw $9, 0x88($8) */
+ bl_gen_writel(&p, cm_base,
+ cpu_mips_phys_to_kseg1(NULL, GCR_BASE_ADDR +
GCR_BASE_OFS));
+ bl_gen_writel(&p, gic_base | GCR_GIC_BASE_GICEN_MSK,
+ cpu_mips_phys_to_kseg1(NULL, cm_base + GCR_GIC_BASE_OFS));
+ bl_gen_writel(&p, cpc_base | GCR_CPC_BASE_CPCEN_MSK,
+ cpu_mips_phys_to_kseg1(NULL, cm_base + GCR_CPC_BASE_OFS));
}
/*
@@ -325,21 +305,7 @@ static void gen_firmware(uint32_t *p, hwaddr kernel_entry,
hwaddr fdt_addr,
* a2/$6 = 0
* a3/$7 = 0
*/
- stl_p(p++, 0x2404fffe); /* li $4, -2 */
- /* lui $5, hi(fdt_addr) */
- stl_p(p++, 0x3c050000 | ((fdt_addr >> 16) & 0xffff));
- if (fdt_addr & 0xffff) { /* ori $5, lo(fdt_addr) */
- stl_p(p++, 0x34a50000 | (fdt_addr & 0xffff));
- }
- stl_p(p++, 0x34060000); /* li $6, 0 */
- stl_p(p++, 0x34070000); /* li $7, 0 */
-
- /* Load kernel entry address & jump to it */
- /* lui $25, hi(kernel_entry)
*/
- stl_p(p++, 0x3c190000 | ((kernel_entry >> 16) & 0xffff));
- /* ori $25, lo(kernel_entry)
*/
- stl_p(p++, 0x37390000 | (kernel_entry & 0xffff));
- stl_p(p++, 0x03200009); /* jr $25 */
+ bl_gen_jump_kernel(&p, 0, -2, fdt_addr, 0, 0, kernel_entry);
}
static const void *boston_fdt_filter(void *opaque, const void *fdt_orig,
--
2.29.2
- [PATCH 0/5] MIPS Bootloader helper, Jiaxun Yang, 2020/12/07
- [PATCH 3/5] hw/mips/fuloong2e: Make use of bootloader helper, Jiaxun Yang, 2020/12/07
- [PATCH 1/5] hw/mips: Add a bootloader helper, Jiaxun Yang, 2020/12/07
- [PATCH 2/5] hw/mips/malta: Make use of bootloader helper, Jiaxun Yang, 2020/12/07
- [PATCH 4/5] hw/mips/addr: Add translation helpers for KSEG1, Jiaxun Yang, 2020/12/07
- [PATCH 5/5] hw/mips/boston: Make use of bootloader helper,
Jiaxun Yang <=
- Re: [PATCH 0/5] MIPS Bootloader helper, Philippe Mathieu-Daudé, 2020/12/07