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[PULL 08/36] i.MX25: Fix bad printf format specifiers
From: |
Peter Maydell |
Subject: |
[PULL 08/36] i.MX25: Fix bad printf format specifiers |
Date: |
Thu, 10 Dec 2020 11:47:28 +0000 |
From: Alex Chen <alex.chen@huawei.com>
We should use printf format specifier "%u" instead of "%d" for
argument of type "unsigned int".
Reported-by: Euler Robot <euler.robot@huawei.com>
Signed-off-by: Alex Chen <alex.chen@huawei.com>
Message-id: 20201126111109.112238-2-alex.chen@huawei.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/misc/imx25_ccm.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/hw/misc/imx25_ccm.c b/hw/misc/imx25_ccm.c
index d3107e5ca29..ff996e2f2ca 100644
--- a/hw/misc/imx25_ccm.c
+++ b/hw/misc/imx25_ccm.c
@@ -91,7 +91,7 @@ static const char *imx25_ccm_reg_name(uint32_t reg)
case IMX25_CCM_LPIMR1_REG:
return "lpimr1";
default:
- sprintf(unknown, "[%d ?]", reg);
+ sprintf(unknown, "[%u ?]", reg);
return unknown;
}
}
@@ -118,7 +118,7 @@ static uint32_t imx25_ccm_get_mpll_clk(IMXCCMState *dev)
freq = imx_ccm_calc_pll(s->reg[IMX25_CCM_MPCTL_REG], CKIH_FREQ);
}
- DPRINTF("freq = %d\n", freq);
+ DPRINTF("freq = %u\n", freq);
return freq;
}
@@ -136,7 +136,7 @@ static uint32_t imx25_ccm_get_mcu_clk(IMXCCMState *dev)
freq = freq / (1 + EXTRACT(s->reg[IMX25_CCM_CCTL_REG], ARM_CLK_DIV));
- DPRINTF("freq = %d\n", freq);
+ DPRINTF("freq = %u\n", freq);
return freq;
}
@@ -149,7 +149,7 @@ static uint32_t imx25_ccm_get_ahb_clk(IMXCCMState *dev)
freq = imx25_ccm_get_mcu_clk(dev)
/ (1 + EXTRACT(s->reg[IMX25_CCM_CCTL_REG], AHB_CLK_DIV));
- DPRINTF("freq = %d\n", freq);
+ DPRINTF("freq = %u\n", freq);
return freq;
}
@@ -160,7 +160,7 @@ static uint32_t imx25_ccm_get_ipg_clk(IMXCCMState *dev)
freq = imx25_ccm_get_ahb_clk(dev) / 2;
- DPRINTF("freq = %d\n", freq);
+ DPRINTF("freq = %u\n", freq);
return freq;
}
@@ -186,7 +186,7 @@ static uint32_t imx25_ccm_get_clock_frequency(IMXCCMState
*dev, IMXClk clock)
break;
}
- DPRINTF("Clock = %d) = %d\n", clock, freq);
+ DPRINTF("Clock = %d) = %u\n", clock, freq);
return freq;
}
--
2.20.1
- [PULL 00/36] target-arm queue, Peter Maydell, 2020/12/10
- [PULL 03/36] xlnx-zynqmp: Connect Xilinx ZynqMP CAN controllers, Peter Maydell, 2020/12/10
- [PULL 06/36] sbsa-ref: allow to use Cortex-A53/57/72 cpus, Peter Maydell, 2020/12/10
- [PULL 01/36] hw/arm/smmuv3: Fix up L1STD_SPAN decoding, Peter Maydell, 2020/12/10
- [PULL 05/36] MAINTAINERS: Add maintainer entry for Xilinx ZynqMP CAN controller, Peter Maydell, 2020/12/10
- [PULL 04/36] tests/qtest: Introduce tests for Xilinx ZynqMP CAN controller, Peter Maydell, 2020/12/10
- [PULL 02/36] hw/net/can: Introduce Xilinx ZynqMP CAN controller, Peter Maydell, 2020/12/10
- [PULL 09/36] i.MX31: Fix bad printf format specifiers, Peter Maydell, 2020/12/10
- [PULL 07/36] tests/qtest/npcm7xx_rng-test: dump random data on failure, Peter Maydell, 2020/12/10
- [PULL 14/36] target/arm: Don't clobber ID_PFR1.Security on M-profile cores, Peter Maydell, 2020/12/10
- [PULL 08/36] i.MX25: Fix bad printf format specifiers,
Peter Maydell <=
- [PULL 10/36] i.MX6: Fix bad printf format specifiers, Peter Maydell, 2020/12/10
- [PULL 16/36] target/arm: Implement CLRM instruction, Peter Maydell, 2020/12/10
- [PULL 17/36] target/arm: Enforce M-profile VMRS/VMSR register restrictions, Peter Maydell, 2020/12/10
- [PULL 11/36] i.MX6ul: Fix bad printf format specifiers, Peter Maydell, 2020/12/10
- [PULL 13/36] target/arm: Implement v8.1M PXN extension, Peter Maydell, 2020/12/10
- [PULL 15/36] target/arm: Implement VSCCLRM insn, Peter Maydell, 2020/12/10
- [PULL 21/36] target/arm: Implement M-profile FPSCR_nzcvqc, Peter Maydell, 2020/12/10
- [PULL 25/36] hw/intc/armv7m_nvic: Update FPDSCR masking for v8.1M, Peter Maydell, 2020/12/10
- [PULL 22/36] target/arm: Use new FPCR_NZCV_MASK constant, Peter Maydell, 2020/12/10
- [PULL 19/36] target/arm: Move general-use constant expanders up in translate.c, Peter Maydell, 2020/12/10