[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH v4 04/43] util: Specialize flush_idcache_range for aarch64
From: |
Richard Henderson |
Subject: |
[PATCH v4 04/43] util: Specialize flush_idcache_range for aarch64 |
Date: |
Mon, 14 Dec 2020 08:02:35 -0600 |
For darwin, the CTR_EL0 register is not accessible, but there
are system routines that we can use.
For other hosts, copy the single pointer implementation from
libgcc and modify it to support the double pointer interface
we require. This halves the number of cache operations required
when split-rwx is enabled.
Cc: Joelle van Dyne <j@getutm.app>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
util/cacheflush.c | 69 +++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 69 insertions(+)
diff --git a/util/cacheflush.c b/util/cacheflush.c
index 92805efe49..6a20723902 100644
--- a/util/cacheflush.c
+++ b/util/cacheflush.c
@@ -7,12 +7,81 @@
#include "qemu/osdep.h"
#include "qemu/cacheflush.h"
+#include "qemu/bitops.h"
#if defined(__i386__) || defined(__x86_64__) || defined(__s390__)
/* Caches are coherent and do not require flushing; symbol inline. */
+#elif defined(__aarch64__)
+
+#ifdef CONFIG_DARWIN
+/* Apple does not expose CTR_EL0, so we must use system interfaces. */
+extern void sys_icache_invalidate(void *start, size_t len);
+extern void sys_dcache_flush(void *start, size_t len);
+void flush_idcache_range(uintptr_t rx, uintptr_t rw, size_t len)
+{
+ sys_dcache_flush((void *)rw, len);
+ sys_icache_invalidate((void *)rx, len);
+}
+#else
+
+/*
+ * TODO: unify this with cacheinfo.c.
+ * We want to save the whole contents of CTR_EL0, so that we
+ * have more than the linesize, but also IDC and DIC.
+ */
+static unsigned int save_ctr_el0;
+static void __attribute__((constructor)) init_ctr_el0(void)
+{
+ asm volatile("mrs\t%0, ctr_el0" : "=r"(save_ctr_el0));
+}
+
+/*
+ * This is a copy of gcc's __aarch64_sync_cache_range, modified
+ * to fit this three-operand interface.
+ */
+void flush_idcache_range(uintptr_t rx, uintptr_t rw, size_t len)
+{
+ const unsigned CTR_IDC = 1u << 28;
+ const unsigned CTR_DIC = 1u << 29;
+ const unsigned int ctr_el0 = save_ctr_el0;
+ const uintptr_t icache_lsize = 4 << extract32(ctr_el0, 0, 4);
+ const uintptr_t dcache_lsize = 4 << extract32(ctr_el0, 16, 4);
+ uintptr_t p;
+
+ /*
+ * If CTR_EL0.IDC is enabled, Data cache clean to the Point of Unification
+ * is not required for instruction to data coherence.
+ */
+ if (!(ctr_el0 & CTR_IDC)) {
+ /*
+ * Loop over the address range, clearing one cache line at once.
+ * Data cache must be flushed to unification first to make sure
+ * the instruction cache fetches the updated data.
+ */
+ for (p = rw & -dcache_lsize; p < rw + len; p += dcache_lsize) {
+ asm volatile("dc\tcvau, %0" : : "r" (p) : "memory");
+ }
+ asm volatile("dsb\tish" : : : "memory");
+ }
+
+ /*
+ * If CTR_EL0.DIC is enabled, Instruction cache cleaning to the Point
+ * of Unification is not required for instruction to data coherence.
+ */
+ if (!(ctr_el0 & CTR_DIC)) {
+ for (p = rx & -icache_lsize; p < rx + len; p += icache_lsize) {
+ asm volatile("ic\tivau, %0" : : "r"(p) : "memory");
+ }
+ asm volatile ("dsb\tish" : : : "memory");
+ }
+
+ asm volatile("isb" : : : "memory");
+}
+#endif /* CONFIG_DARWIN */
+
#elif defined(__mips__)
#ifdef __OpenBSD__
--
2.25.1
- [PATCH v4 00/43] Mirror map JIT memory for TCG, Richard Henderson, 2020/12/14
- [PATCH v4 02/43] util: Extract flush_icache_range to cacheflush.c, Richard Henderson, 2020/12/14
- [PATCH v4 03/43] util: Enhance flush_icache_range with separate data pointer, Richard Henderson, 2020/12/14
- [PATCH v4 04/43] util: Specialize flush_idcache_range for aarch64,
Richard Henderson <=
- [PATCH v4 01/43] tcg: Do not flush icache for interpreter, Richard Henderson, 2020/12/14
- [PATCH v4 05/43] tcg: Move tcg prologue pointer out of TCGContext, Richard Henderson, 2020/12/14
- [PATCH v4 06/43] tcg: Move tcg epilogue pointer out of TCGContext, Richard Henderson, 2020/12/14
- [PATCH v4 07/43] tcg: Add in_code_gen_buffer, Richard Henderson, 2020/12/14