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[PATCH v2 07/24] target/mips: Simplify MSA TCG logic
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From: |
Philippe Mathieu-Daudé |
|
Subject: |
[PATCH v2 07/24] target/mips: Simplify MSA TCG logic |
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Date: |
Tue, 15 Dec 2020 23:57:40 +0100 |
Only decode MSA opcodes if MSA is present (implemented).
Now than check_msa_access() will only be called if MSA is
present, the only way to have MIPS_HFLAG_MSA unset is if
MSA is disabled (bit CP0C5_MSAEn cleared, see previous
commit). Therefore we can remove the 'reserved instruction'
exception.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/translate.c | 22 ++++++++++------------
1 file changed, 10 insertions(+), 12 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index fc658b3be33..02ea184f9a3 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -28568,13 +28568,8 @@ static inline int check_msa_access(DisasContext *ctx)
}
if (unlikely(!(ctx->hflags & MIPS_HFLAG_MSA))) {
- if (ctx->insn_flags & ASE_MSA) {
- generate_exception_end(ctx, EXCP_MSADIS);
- return 0;
- } else {
- gen_reserved_instruction(ctx);
- return 0;
- }
+ generate_exception_end(ctx, EXCP_MSADIS);
+ return 0;
}
return 1;
}
@@ -30418,7 +30413,7 @@ static void gen_msa_vec(CPUMIPSState *env, DisasContext
*ctx)
static void gen_msa(CPUMIPSState *env, DisasContext *ctx)
{
uint32_t opcode = ctx->opcode;
- check_insn(ctx, ASE_MSA);
+
check_msa_access(ctx);
switch (MASK_MSA_MINOR(opcode)) {
@@ -31048,9 +31043,10 @@ static bool decode_opc_legacy(CPUMIPSState *env,
DisasContext *ctx)
case OPC_BNZ_H:
case OPC_BNZ_W:
case OPC_BNZ_D:
- check_insn(ctx, ASE_MSA);
- gen_msa_branch(env, ctx, op1);
- break;
+ if (ase_msa_available(env)) {
+ gen_msa_branch(env, ctx, op1);
+ break;
+ }
default:
MIPS_INVAL("cp1");
gen_reserved_instruction(ctx);
@@ -31239,7 +31235,9 @@ static bool decode_opc_legacy(CPUMIPSState *env,
DisasContext *ctx)
#endif
} else {
/* MDMX: Not implemented. */
- gen_msa(env, ctx);
+ if (ase_msa_available(env)) {
+ gen_msa(env, ctx);
+ }
}
break;
case OPC_PCREL:
--
2.26.2
- [PATCH v2 00/24] target/mips: Convert MSA ASE to decodetree, Philippe Mathieu-Daudé, 2020/12/15
- [PATCH v2 01/24] target/mips/translate: Extract decode_opc_legacy() from decode_opc(), Philippe Mathieu-Daudé, 2020/12/15
- [PATCH v2 02/24] target/mips/translate: Expose check_mips_64() to 32-bit mode, Philippe Mathieu-Daudé, 2020/12/15
- [PATCH v2 03/24] target/mips/cpu: Introduce isa_rel6_available() helper, Philippe Mathieu-Daudé, 2020/12/15
- [PATCH v2 04/24] target/mips: Introduce ase_msa_available() helper, Philippe Mathieu-Daudé, 2020/12/15
- [PATCH v2 05/24] target/mips: Simplify msa_reset(), Philippe Mathieu-Daudé, 2020/12/15
- [PATCH v2 06/24] target/mips: Use CP0_Config3 to set MIPS_HFLAG_MSA, Philippe Mathieu-Daudé, 2020/12/15
- [PATCH v2 07/24] target/mips: Simplify MSA TCG logic,
Philippe Mathieu-Daudé <=
- [PATCH v2 08/24] target/mips: Remove now unused ASE_MSA definition, Philippe Mathieu-Daudé, 2020/12/15
- [PATCH v2 09/24] target/mips: Alias MSA vector registers on FPU scalar registers, Philippe Mathieu-Daudé, 2020/12/15
- [PATCH v2 10/24] target/mips: Extract msa_translate_init() from mips_tcg_init(), Philippe Mathieu-Daudé, 2020/12/15
- [PATCH v2 11/24] target/mips: Remove CPUMIPSState* argument from gen_msa*() methods, Philippe Mathieu-Daudé, 2020/12/15
- [PATCH v2 12/24] target/mips: Explode gen_msa_branch() as gen_msa_BxZ_V/BxZ(), Philippe Mathieu-Daudé, 2020/12/15
- [PATCH v2 13/24] target/mips: Rename msa_helper.c as mod-msa_helper.c, Philippe Mathieu-Daudé, 2020/12/15
- [PATCH v2 14/24] target/mips: Move msa_reset() to mod-msa_helper.c, Philippe Mathieu-Daudé, 2020/12/15
- [PATCH v2 15/24] target/mips: Extract MSA helpers from op_helper.c, Philippe Mathieu-Daudé, 2020/12/15
- [PATCH v2 16/24] target/mips: Extract MSA helper definitions, Philippe Mathieu-Daudé, 2020/12/15