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[RFC v2 10/15] target/riscv: rvb: rotate (left/right)
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From: |
frank . chang |
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Subject: |
[RFC v2 10/15] target/riscv: rvb: rotate (left/right) |
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Date: |
Wed, 16 Dec 2020 10:01:35 +0800 |
From: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn32-64.decode | 3 ++
target/riscv/insn32.decode | 3 ++
target/riscv/insn_trans/trans_rvb.c.inc | 61 +++++++++++++++++++++++++
target/riscv/translate.c | 36 +++++++++++++++
4 files changed, 103 insertions(+)
diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
index 6d017c70c74..ac0634d754a 100644
--- a/target/riscv/insn32-64.decode
+++ b/target/riscv/insn32-64.decode
@@ -100,9 +100,12 @@ sbinvw 0110100 .......... 001 ..... 0111011 @r
sbextw 0100100 .......... 101 ..... 0111011 @r
slow 0010000 .......... 001 ..... 0111011 @r
srow 0010000 .......... 101 ..... 0111011 @r
+rorw 0110000 .......... 101 ..... 0111011 @r
+rolw 0110000 .......... 001 ..... 0111011 @r
sbsetiw 0010100 .......... 001 ..... 0011011 @sh5
sbclriw 0100100 .......... 001 ..... 0011011 @sh5
sbinviw 0110100 .......... 001 ..... 0011011 @sh5
sloiw 0010000 .......... 001 ..... 0011011 @sh5
sroiw 0010000 .......... 101 ..... 0011011 @sh5
+roriw 0110000 .......... 101 ..... 0011011 @sh5
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 78ce4b11097..b4677293582 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -617,6 +617,8 @@ sbinv 0110100 .......... 001 ..... 0110011 @r
sbext 0100100 .......... 101 ..... 0110011 @r
slo 0010000 .......... 001 ..... 0110011 @r
sro 0010000 .......... 101 ..... 0110011 @r
+ror 0110000 .......... 101 ..... 0110011 @r
+rol 0110000 .......... 001 ..... 0110011 @r
sbseti 00101. ........... 001 ..... 0010011 @sh
sbclri 01001. ........... 001 ..... 0010011 @sh
@@ -624,3 +626,4 @@ sbinvi 01101. ........... 001 ..... 0010011 @sh
sbexti 01001. ........... 101 ..... 0010011 @sh
sloi 00100. ........... 001 ..... 0010011 @sh
sroi 00100. ........... 101 ..... 0010011 @sh
+rori 01100. ........... 101 ..... 0010011 @sh
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc
b/target/riscv/insn_trans/trans_rvb.c.inc
index 11b5439e703..433cc7f9fc8 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -189,7 +189,36 @@ static bool trans_sroi(DisasContext *ctx, arg_sroi *a)
return gen_shifti(ctx, a, &gen_sro);
}
+static bool trans_ror(DisasContext *ctx, arg_ror *a)
{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_arith(ctx, a, &tcg_gen_rotr_tl);
+}
+
+static bool trans_rori(DisasContext *ctx, arg_rori *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+
+ if (a->shamt >= TARGET_LONG_BITS) {
+ return false;
+ }
+
+ TCGv source1 = tcg_temp_new();
+
+ gen_get_gpr(source1, a->rs1);
+ tcg_gen_rotri_tl(source1, source1, a->shamt);
+ gen_set_gpr(a->rd, source1);
+
+ tcg_temp_free(source1);
+ return true;
+}
+
+static bool trans_rol(DisasContext *ctx, arg_rol *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_arith(ctx, a, &tcg_gen_rotl_tl);
+}
+
/* RV64-only instructions */
#ifdef TARGET_RISCV64
@@ -289,4 +318,36 @@ static bool trans_sroiw(DisasContext *ctx, arg_sroiw *a)
return gen_shiftiw(ctx, a, &gen_sro);
}
+static bool trans_rorw(DisasContext *ctx, arg_rorw *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shiftw(ctx, a, &gen_rorw);
+}
+
+static bool trans_roriw(DisasContext *ctx, arg_roriw *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+
+ if (a->shamt >= 32) {
+ return false;
+ }
+
+ if (a->shamt == 0) {
+ TCGv t = tcg_temp_new();
+ gen_get_gpr(t, a->rs1);
+ tcg_gen_ext32s_tl(t, t);
+ gen_set_gpr(a->rd, t);
+ tcg_temp_free(t);
+ return true;
+ }
+
+ return gen_shiftiw(ctx, a, &gen_rorw);
+}
+
+static bool trans_rolw(DisasContext *ctx, arg_rolw *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shiftw(ctx, a, &gen_rolw);
+}
+
#endif
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 0c00d20ab1b..10b4142a3ab 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -849,6 +849,42 @@ static void gen_packuw(TCGv ret, TCGv arg1, TCGv arg2)
tcg_temp_free(t);
}
+static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2)
+{
+ TCGv_i32 t1 = tcg_temp_new_i32();
+ TCGv_i32 t2 = tcg_temp_new_i32();
+
+ /* truncate to 32-bits */
+ tcg_gen_trunc_tl_i32(t1, arg1);
+ tcg_gen_trunc_tl_i32(t2, arg2);
+
+ tcg_gen_rotr_i32(t1, t1, t2);
+
+ /* sign-extend 64-bits */
+ tcg_gen_ext_i32_tl(ret, t1);
+
+ tcg_temp_free_i32(t1);
+ tcg_temp_free_i32(t2);
+}
+
+static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2)
+{
+ TCGv_i32 t1 = tcg_temp_new_i32();
+ TCGv_i32 t2 = tcg_temp_new_i32();
+
+ /* truncate to 32-bits */
+ tcg_gen_trunc_tl_i32(t1, arg1);
+ tcg_gen_trunc_tl_i32(t2, arg2);
+
+ tcg_gen_rotl_i32(t1, t1, t2);
+
+ /* sign-extend 64-bits */
+ tcg_gen_ext_i32_tl(ret, t1);
+
+ tcg_temp_free_i32(t1);
+ tcg_temp_free_i32(t2);
+}
+
#endif
static bool gen_arith(DisasContext *ctx, arg_r *a,
--
2.17.1
- [RFC v2 05/15] target/riscv: rvb: pack two words into one register, (continued)
- [RFC v2 05/15] target/riscv: rvb: pack two words into one register, frank . chang, 2020/12/15
- [RFC v2 06/15] target/riscv: rvb: min/max instructions, frank . chang, 2020/12/15
- [RFC v2 07/15] target/riscv: rvb: sign-extend instructions, frank . chang, 2020/12/15
- [RFC v2 08/15] target/riscv: rvb: single-bit instructions, frank . chang, 2020/12/15
- [RFC v2 09/15] target/riscv: rvb: shift ones, frank . chang, 2020/12/15
- [RFC v2 10/15] target/riscv: rvb: rotate (left/right),
frank . chang <=
- [RFC v2 12/15] target/riscv: rvb: generalized or-combine, frank . chang, 2020/12/15
- [RFC v2 13/15] target/riscv: rvb: address calculation, frank . chang, 2020/12/15
- [RFC v2 14/15] target/riscv: rvb: add/sub with postfix zero-extend, frank . chang, 2020/12/15
- [RFC v2 11/15] target/riscv: rvb: generalized reverse, frank . chang, 2020/12/15
- [RFC v2 15/15] target/riscv: rvb: support and turn on B-extension from command line, frank . chang, 2020/12/15