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[PATCH v2 6/7] target/ppc: Add support for prefixed load/store FP instru
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From: |
Gustavo Romero |
|
Subject: |
[PATCH v2 6/7] target/ppc: Add support for prefixed load/store FP instructions |
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Date: |
Wed, 16 Dec 2020 06:08:03 -0300 |
From: Michael Roth <mdroth@linux.vnet.ibm.com>
This commit adds support for the following load/store instructions for FP
registers:
plf, plfd
pstfs, pstfd
Signed-off-by: Michael Roth <mroth@lamentation.net>
Signed-off-by: Gustavo Romero <gromero@linux.ibm.com>
---
target/ppc/translate/fp-impl.c.inc | 48 ++++++++++++++++++++++++++++++
target/ppc/translate/fp-ops.c.inc | 6 ++++
2 files changed, 54 insertions(+)
diff --git a/target/ppc/translate/fp-impl.c.inc
b/target/ppc/translate/fp-impl.c.inc
index 9f7868ee28..1eec98de0f 100644
--- a/target/ppc/translate/fp-impl.c.inc
+++ b/target/ppc/translate/fp-impl.c.inc
@@ -874,6 +874,28 @@ static void glue(gen_, name)(DisasContext *ctx)
\
tcg_temp_free_i64(t0); \
}
+#define GEN_PLDF(name, ldop, opc, type) \
+static void glue(gen_, p##name)(DisasContext *ctx) \
+{ \
+ TCGv EA; \
+ TCGv_i64 t0; \
+ if (unlikely(!ctx->fpu_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_FPU); \
+ return; \
+ } \
+ gen_set_access_type(ctx, ACCESS_FLOAT); \
+ EA = tcg_temp_new(); \
+ t0 = tcg_temp_new_i64(); \
+ if (gen_addr_imm34_index(ctx, EA)) { \
+ goto out; \
+ } \
+ gen_qemu_##ldop(ctx, t0, EA); \
+ set_fpr(rD(ctx->opcode), t0); \
+out: \
+ tcg_temp_free(EA); \
+ tcg_temp_free_i64(t0); \
+}
+
#define GEN_LDUF(name, ldop, opc, type) \
static void glue(gen_, name##u)(DisasContext *ctx) \
{ \
@@ -943,6 +965,7 @@ static void glue(gen_, name##x)(DisasContext *ctx)
\
#define GEN_LDFS(name, ldop, op, type) \
GEN_LDF(name, ldop, op | 0x20, type); \
+GEN_PLDF(name, ldop, op | 0x20, type); \
GEN_LDUF(name, ldop, op | 0x21, type); \
GEN_LDUXF(name, ldop, op | 0x01, type); \
GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
@@ -1109,6 +1132,28 @@ static void glue(gen_, name)(DisasContext *ctx)
\
tcg_temp_free_i64(t0); \
}
+#define GEN_PSTF(name, stop, opc, type) \
+static void glue(gen_, p##name)(DisasContext *ctx)
\
+{ \
+ TCGv EA; \
+ TCGv_i64 t0; \
+ if (unlikely(!ctx->fpu_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_FPU); \
+ return; \
+ } \
+ gen_set_access_type(ctx, ACCESS_FLOAT); \
+ EA = tcg_temp_new(); \
+ t0 = tcg_temp_new_i64(); \
+ if (gen_addr_imm34_index(ctx, EA)) { \
+ goto out; \
+ } \
+ get_fpr(t0, rS(ctx->opcode)); \
+ gen_qemu_##stop(ctx, t0, EA); \
+out: \
+ tcg_temp_free(EA); \
+ tcg_temp_free_i64(t0); \
+}
+
#define GEN_STUF(name, stop, opc, type) \
static void glue(gen_, name##u)(DisasContext *ctx) \
{ \
@@ -1178,6 +1223,7 @@ static void glue(gen_, name##x)(DisasContext *ctx)
\
#define GEN_STFS(name, stop, op, type) \
GEN_STF(name, stop, op | 0x20, type); \
+GEN_PSTF(name, stop, op | 0x20, type); \
GEN_STUF(name, stop, op | 0x21, type); \
GEN_STUXF(name, stop, op | 0x01, type); \
GEN_STXF(name, stop, 0x17, op | 0x00, type)
@@ -1483,12 +1529,14 @@ static void gen_stfqx(DisasContext *ctx)
#undef GEN_FLOAT_BS
#undef GEN_LDF
+#undef GEN_PLDF
#undef GEN_LDUF
#undef GEN_LDUXF
#undef GEN_LDXF
#undef GEN_LDFS
#undef GEN_STF
+#undef GEN_PSTF
#undef GEN_STUF
#undef GEN_STUXF
#undef GEN_STXF
diff --git a/target/ppc/translate/fp-ops.c.inc
b/target/ppc/translate/fp-ops.c.inc
index 88fab65628..fed0db8f65 100644
--- a/target/ppc/translate/fp-ops.c.inc
+++ b/target/ppc/translate/fp-ops.c.inc
@@ -52,6 +52,8 @@ GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT),
#define GEN_LDF(name, ldop, opc, type) \
GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
+#define GEN_PLDF(name, ldop, opc, type) \
+GEN_HANDLER_E_PREFIXED_M(p##name, opc, 0xFF, 0xFF, 0x0, PPC_64B, PPC2_ISA310),
#define GEN_LDUF(name, ldop, opc, type) \
GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
#define GEN_LDUXF(name, ldop, opc, type) \
@@ -60,6 +62,7 @@ GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
#define GEN_LDFS(name, ldop, op, type) \
GEN_LDF(name, ldop, op | 0x20, type) \
+GEN_PLDF(name, ldop, op | 0x20, type) \
GEN_LDUF(name, ldop, op | 0x21, type) \
GEN_LDUXF(name, ldop, op | 0x01, type) \
GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
@@ -73,6 +76,8 @@ GEN_HANDLER_E(lfdpx, 0x1F, 0x17, 0x18, 0x00200001, PPC_NONE,
PPC2_ISA205),
#define GEN_STF(name, stop, opc, type) \
GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
+#define GEN_PSTF(name, ldop, opc, type) \
+GEN_HANDLER_E_PREFIXED_M(p##name, opc, 0xFF, 0xFF, 0x0, PPC_64B, PPC2_ISA310),
#define GEN_STUF(name, stop, opc, type) \
GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
#define GEN_STUXF(name, stop, opc, type) \
@@ -81,6 +86,7 @@ GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
#define GEN_STFS(name, stop, op, type) \
GEN_STF(name, stop, op | 0x20, type) \
+GEN_PSTF(name, stop, op | 0x20, type) \
GEN_STUF(name, stop, op | 0x21, type) \
GEN_STUXF(name, stop, op | 0x01, type) \
GEN_STXF(name, stop, 0x17, op | 0x00, type)
--
2.17.1
- [PATCH v2 0/7] PPC64: Add support for the new prefixed instructions, Gustavo Romero, 2020/12/16
- [PATCH v2 1/7] target/ppc: Add infrastructure for prefixed instructions, Gustavo Romero, 2020/12/16
- [PATCH v2 3/7] tests/tcg: Add tests for prefixed load/store instructions, Gustavo Romero, 2020/12/16
- [PATCH v2 2/7] target/ppc: Add support for prefixed load/store instructions, Gustavo Romero, 2020/12/16
- [PATCH v2 4/7] target/ppc: Add support for paired vector load/store instructions, Gustavo Romero, 2020/12/16
- [PATCH v2 5/7] tests/tcg: Add tests for paired vector load/store instructions, Gustavo Romero, 2020/12/16
- [PATCH v2 6/7] target/ppc: Add support for prefixed load/store FP instructions,
Gustavo Romero <=
- [PATCH v2 7/7] tests/tcg: Add tests for prefixed load/store FP instructions, Gustavo Romero, 2020/12/16
- Re: [PATCH v2 0/7] PPC64: Add support for the new prefixed instructions, no-reply, 2020/12/16