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RE: [PATCH v2] i386: Add the support for AMD EPYC 3rd generation process
From: |
Babu Moger |
Subject: |
RE: [PATCH v2] i386: Add the support for AMD EPYC 3rd generation processors |
Date: |
Mon, 1 Mar 2021 13:45:47 -0600 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 |
Pankaj,
> -----Original Message-----
> From: Pankaj Gupta <pankaj.gupta@cloud.ionos.com>
> Sent: Monday, March 1, 2021 10:46 AM
> To: Pankaj Gupta <pankaj.gupta.linux@gmail.com>
> Cc: Moger, Babu <Babu.Moger@amd.com>; Paolo Bonzini
> <pbonzini@redhat.com>; richard.henderson@linaro.org; Eduardo Habkost
> <ehabkost@redhat.com>; Qemu Developers <qemu-devel@nongnu.org>
> Subject: Re: [PATCH v2] i386: Add the support for AMD EPYC 3rd generation
> processors
>
> Hi Babu,
>
> I tried to test below patch for AMD EPYC Rome CPU and I got below error [1]:
>
> Also, I noticed SSBD CPU flag for guest was still available even without this
> patch, I noticed that for the guest, AMD_SSBD not got set.
>
> Guest:
> 0x80000008 0x00: eax=0x00003028 ebx=0x00009205 ecx=0x00002003
> edx=0x00000000
>
> [1]
> [ 0.008000] unchecked MSR access error: WRMSR to 0x48 (tried to
> write 0x0000000000000000) at rIP: 0xffffffff9245c9e4
> (native_write_msr+0x4/0x20)
> [ 0.008000] [<ffffffff9243a6c5>] ? x86_spec_ctrl_setup_ap+0x35/0x50
> [ 0.008000] [<ffffffff92439423>] ? identify_secondary_cpu+0x53/0x80
> [ 0.008000] [<ffffffff9244adfa>] ? start_secondary+0x6a/0x1b0
>
> 0.011970] unchecked MSR access error: RDMSR from 0x48 at rIP:
> 0xffffffff9245c772 (native_read_msr+0x2/0x40)
I did not see any problem with these patches.
My guest setup.
# lscpu |grep -o ssbd
ssbd
[root@rome-vm ~]# uname -r
4.18.0-147.el8.x86_64
[root@rome-vm ~]# cat /etc/redhat-release
Red Hat Enterprise Linux release 8.1 (Ootpa)
# wrmsr 0x48 7
[root@rome-vm ~]# rdmsr 0x48
7
My host os.
# uname -r
4.18.0-193.el8.x86_64
[root@rome images]# cat /etc/redhat-release
Red Hat Enterprise Linux release 8.2 Beta (Ootpa)
Also, I only see ssbd feature when add this patch(EPYC-Rome-v2).
Otherwise, I don’t see ssbd feature.
Thanks
Babu
>
> Thanks,
> Pankaj
>
> > > It is normally added as v2 for compatibility. Like this.
> >
> > o.k. Thanks!
> > I will test this tomorrow.
> >
> > >
> > > diff --git a/target/i386/cpu.c b/target/i386/cpu.c index
> > > 24db7ed892..f721d0db78 100644
> > > --- a/target/i386/cpu.c
> > > +++ b/target/i386/cpu.c
> > > @@ -4179,6 +4179,20 @@ static X86CPUDefinition builtin_x86_defs[] = {
> > > .xlevel = 0x8000001E,
> > > .model_id = "AMD EPYC-Rome Processor",
> > > .cache_info = &epyc_rome_cache_info,
> > > + .versions = (X86CPUVersionDefinition[]) {
> > > + { .version = 1 },
> > > + {
> > > + .version = 2,
> > > + .props = (PropValue[]) {
> > > + { "ibrs", "on" },
> > > + { "amd-ssbd", "on" },
> > > + { "model-id",
> > > + "AMD EPYC-Rome Processor" },
> > > + { /* end of list */ }
> > > + }
> > > + },
> > > + { /* end of list */ }
> > > + }
> > > },
> > > {
> > > .name = "EPYC-Milan",