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[PATCH 11/27] tcg/tci: Merge identical cases in generation (load/store o
From: |
Richard Henderson |
Subject: |
[PATCH 11/27] tcg/tci: Merge identical cases in generation (load/store opcodes) |
Date: |
Tue, 2 Mar 2021 09:57:25 -0800 |
Use CASE_32_64 and CASE_64 to reduce ifdefs and merge
cases that are identical between 32-bit and 64-bit hosts.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210217202036.1724901-5-richard.henderson@linaro.org>
[PMD: Split patch as 5/5]
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210218232840.1760806-6-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci/tcg-target.c.inc | 49 ++++++++++++----------------------------
1 file changed, 14 insertions(+), 35 deletions(-)
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index f9893b9539..c79f9c32d8 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -440,25 +440,20 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
const TCGArg *args,
tcg_out8(s, args[5]); /* condition */
break;
#endif
- case INDEX_op_ld8u_i32:
- case INDEX_op_ld8s_i32:
- case INDEX_op_ld16u_i32:
- case INDEX_op_ld16s_i32:
+
+ CASE_32_64(ld8u)
+ CASE_32_64(ld8s)
+ CASE_32_64(ld16u)
+ CASE_32_64(ld16s)
case INDEX_op_ld_i32:
- case INDEX_op_st8_i32:
- case INDEX_op_st16_i32:
+ CASE_64(ld32u)
+ CASE_64(ld32s)
+ CASE_64(ld)
+ CASE_32_64(st8)
+ CASE_32_64(st16)
case INDEX_op_st_i32:
- case INDEX_op_ld8u_i64:
- case INDEX_op_ld8s_i64:
- case INDEX_op_ld16u_i64:
- case INDEX_op_ld16s_i64:
- case INDEX_op_ld32u_i64:
- case INDEX_op_ld32s_i64:
- case INDEX_op_ld_i64:
- case INDEX_op_st8_i64:
- case INDEX_op_st16_i64:
- case INDEX_op_st32_i64:
- case INDEX_op_st_i64:
+ CASE_64(st32)
+ CASE_64(st)
stack_bounds_check(args[1], args[2]);
tcg_out_r(s, args[0]);
tcg_out_r(s, args[1]);
@@ -552,24 +547,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const
TCGArg *args,
#endif
case INDEX_op_qemu_ld_i32:
- tcg_out_r(s, *args++);
- tcg_out_r(s, *args++);
- if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) {
- tcg_out_r(s, *args++);
- }
- tcg_out_i(s, *args++);
- break;
- case INDEX_op_qemu_ld_i64:
- tcg_out_r(s, *args++);
- if (TCG_TARGET_REG_BITS == 32) {
- tcg_out_r(s, *args++);
- }
- tcg_out_r(s, *args++);
- if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) {
- tcg_out_r(s, *args++);
- }
- tcg_out_i(s, *args++);
- break;
case INDEX_op_qemu_st_i32:
tcg_out_r(s, *args++);
tcg_out_r(s, *args++);
@@ -578,6 +555,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const
TCGArg *args,
}
tcg_out_i(s, *args++);
break;
+
+ case INDEX_op_qemu_ld_i64:
case INDEX_op_qemu_st_i64:
tcg_out_r(s, *args++);
if (TCG_TARGET_REG_BITS == 32) {
--
2.25.1
- Re: [PATCH 03/27] tcg/aarch64: Fix generation of "scalar" vector operations, (continued)
- [PATCH 04/27] tcg/tci: Use exec/cpu_ldst.h interfaces, Richard Henderson, 2021/03/02
- [PATCH 06/27] tcg: Manage splitwx in tc_ptr_to_region_tree by hand, Richard Henderson, 2021/03/02
- [PATCH 07/27] tcg/tci: Merge identical cases in generation (arithmetic opcodes), Richard Henderson, 2021/03/02
- [PATCH 09/27] tcg/tci: Merge identical cases in generation (deposit opcode), Richard Henderson, 2021/03/02
- [PATCH 08/27] tcg/tci: Merge identical cases in generation (exchange opcodes), Richard Henderson, 2021/03/02
- [PATCH 10/27] tcg/tci: Merge identical cases in generation (conditional opcodes), Richard Henderson, 2021/03/02
- [PATCH 11/27] tcg/tci: Merge identical cases in generation (load/store opcodes),
Richard Henderson <=
- [PATCH 12/27] tcg/tci: Remove tci_read_r8, Richard Henderson, 2021/03/02
- [PATCH 13/27] tcg/tci: Remove tci_read_r8s, Richard Henderson, 2021/03/02
- [PATCH 14/27] tcg/tci: Remove tci_read_r16, Richard Henderson, 2021/03/02
- [PATCH 15/27] tcg/tci: Remove tci_read_r16s, Richard Henderson, 2021/03/02
- [PATCH 16/27] tcg/tci: Remove tci_read_r32, Richard Henderson, 2021/03/02