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[PATCH 20/27] tcg/tci: Merge extension operations
From: |
Richard Henderson |
Subject: |
[PATCH 20/27] tcg/tci: Merge extension operations |
Date: |
Tue, 2 Mar 2021 09:57:34 -0800 |
This includes ext8s, ext8u, ext16s, ext16u.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci.c | 44 ++++++++------------------------------------
1 file changed, 8 insertions(+), 36 deletions(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index d0bf810781..73f639d23a 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -607,29 +607,29 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState
*env,
tci_write_reg64(regs, t1, t0, (uint32_t)t2 * tmp64);
break;
#endif /* TCG_TARGET_REG_BITS == 32 */
-#if TCG_TARGET_HAS_ext8s_i32
- case INDEX_op_ext8s_i32:
+#if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64
+ CASE_32_64(ext8s)
t0 = *tb_ptr++;
t1 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, (int8_t)t1);
break;
#endif
-#if TCG_TARGET_HAS_ext16s_i32
- case INDEX_op_ext16s_i32:
+#if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64
+ CASE_32_64(ext16s)
t0 = *tb_ptr++;
t1 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, (int16_t)t1);
break;
#endif
-#if TCG_TARGET_HAS_ext8u_i32
- case INDEX_op_ext8u_i32:
+#if TCG_TARGET_HAS_ext8u_i32 || TCG_TARGET_HAS_ext8u_i64
+ CASE_32_64(ext8u)
t0 = *tb_ptr++;
t1 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, (uint8_t)t1);
break;
#endif
-#if TCG_TARGET_HAS_ext16u_i32
- case INDEX_op_ext16u_i32:
+#if TCG_TARGET_HAS_ext16u_i32 || TCG_TARGET_HAS_ext16u_i64
+ CASE_32_64(ext16u)
t0 = *tb_ptr++;
t1 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, (uint16_t)t1);
@@ -779,34 +779,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState
*env,
continue;
}
break;
-#if TCG_TARGET_HAS_ext8u_i64
- case INDEX_op_ext8u_i64:
- t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
- tci_write_reg(regs, t0, (uint8_t)t1);
- break;
-#endif
-#if TCG_TARGET_HAS_ext8s_i64
- case INDEX_op_ext8s_i64:
- t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
- tci_write_reg(regs, t0, (int8_t)t1);
- break;
-#endif
-#if TCG_TARGET_HAS_ext16s_i64
- case INDEX_op_ext16s_i64:
- t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
- tci_write_reg(regs, t0, (int16_t)t1);
- break;
-#endif
-#if TCG_TARGET_HAS_ext16u_i64
- case INDEX_op_ext16u_i64:
- t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
- tci_write_reg(regs, t0, (uint16_t)t1);
- break;
-#endif
#if TCG_TARGET_HAS_ext32s_i64
case INDEX_op_ext32s_i64:
#endif
--
2.25.1
- [PATCH 16/27] tcg/tci: Remove tci_read_r32, (continued)
- [PATCH 16/27] tcg/tci: Remove tci_read_r32, Richard Henderson, 2021/03/02
- [PATCH 17/27] tcg/tci: Remove tci_read_r32s, Richard Henderson, 2021/03/02
- [PATCH 18/27] tcg/tci: Reduce use of tci_read_r64, Richard Henderson, 2021/03/02
- [PATCH 22/27] tcg/tci: Merge mov, not and neg operations, Richard Henderson, 2021/03/02
- [PATCH 19/27] tcg/tci: Merge basic arithmetic operations, Richard Henderson, 2021/03/02
- [PATCH 20/27] tcg/tci: Merge extension operations,
Richard Henderson <=
- [PATCH 24/27] accel/tcg: move CF_CLUSTER calculation to curr_cflags, Richard Henderson, 2021/03/02
- [PATCH 23/27] accel/tcg: rename tb_lookup__cpu_state and hoist state extraction, Richard Henderson, 2021/03/02
- [PATCH 21/27] tcg/tci: Merge bswap operations, Richard Henderson, 2021/03/02
- [PATCH 26/27] include/exec: lightly re-arrange TranslationBlock, Richard Henderson, 2021/03/02
- [PATCH 25/27] accel/tcg: drop the use of CF_HASH_MASK and rename params, Richard Henderson, 2021/03/02
- [PATCH 27/27] accel/tcg: Precompute curr_cflags into cpu->tcg_cflags, Richard Henderson, 2021/03/02
- Re: [PATCH 00/27] tcg patch queue, no-reply, 2021/03/02