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[PULL v2 01/19] target/riscv: Declare csr_ops[] with a known size
From: |
Alistair Francis |
Subject: |
[PULL v2 01/19] target/riscv: Declare csr_ops[] with a known size |
Date: |
Thu, 4 Mar 2021 09:46:33 -0500 |
From: Bin Meng <bin.meng@windriver.com>
csr_ops[] is currently declared with an unknown size in cpu.h.
Since the array size is known, let's do a complete declaration.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1611024723-14293-1-git-send-email-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 02758ae0eb..419a21478c 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -487,7 +487,7 @@ enum {
};
/* CSR function table */
-extern riscv_csr_operations csr_ops[];
+extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE];
void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops);
void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops);
--
2.30.1
- [PULL v2 00/19] riscv-to-apply queue, Alistair Francis, 2021/03/04
- [PULL v2 01/19] target/riscv: Declare csr_ops[] with a known size,
Alistair Francis <=
- [PULL v2 02/19] hw/misc: sifive_u_otp: Use error_report() when block operation fails, Alistair Francis, 2021/03/04
- [PULL v2 04/19] target-riscv: support QMP dump-guest-memory, Alistair Francis, 2021/03/04
- [PULL v2 05/19] hw/block: m25p80: Add ISSI SPI flash support, Alistair Francis, 2021/03/04
- [PULL v2 03/19] roms/opensbi: Upgrade from v0.8 to v0.9, Alistair Francis, 2021/03/04
- [PULL v2 06/19] hw/block: m25p80: Add various ISSI flash information, Alistair Francis, 2021/03/04
- [PULL v2 07/19] hw/ssi: Add SiFive SPI controller support, Alistair Francis, 2021/03/04
- [PULL v2 09/19] hw/riscv: sifive_u: Add QSPI2 controller and connect an SD card, Alistair Francis, 2021/03/04
- [PULL v2 08/19] hw/riscv: sifive_u: Add QSPI0 controller and connect a flash, Alistair Francis, 2021/03/04