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[RFC v4 25/33] target/arm: cpu: fix style
From: |
Claudio Fontana |
Subject: |
[RFC v4 25/33] target/arm: cpu: fix style |
Date: |
Fri, 5 Mar 2021 15:59:33 +0100 |
Signed-off-by: Claudio Fontana <cfontana@suse.de>
---
target/arm/cpu-sysemu.c | 17 +++++++++++------
target/arm/cpu32.c | 12 ++++++++----
2 files changed, 19 insertions(+), 10 deletions(-)
diff --git a/target/arm/cpu-sysemu.c b/target/arm/cpu-sysemu.c
index 126263dbf4..eb928832a9 100644
--- a/target/arm/cpu-sysemu.c
+++ b/target/arm/cpu-sysemu.c
@@ -372,7 +372,8 @@ int sve_exception_el(CPUARMState *env, int el)
if (el <= 1 && (hcr_el2 & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) {
bool disabled = false;
- /* The CPACR.ZEN controls traps to EL1:
+ /*
+ * The CPACR.ZEN controls traps to EL1:
* 0, 2 : trap EL0 and EL1 accesses
* 1 : trap only EL0 accesses
* 3 : trap no accesses
@@ -398,7 +399,8 @@ int sve_exception_el(CPUARMState *env, int el)
}
}
- /* CPTR_EL2. Since TZ and TFP are positive,
+ /*
+ * CPTR_EL2. Since TZ and TFP are positive,
* they will be zero when EL2 is not present.
*/
if (el <= 2 && arm_is_el2_enabled(env)) {
@@ -625,10 +627,11 @@ static void arm_cpu_do_interrupt_aarch32(CPUState *cs)
new_mode = ARM_CPU_MODE_UND;
addr = 0x04;
mask = CPSR_I;
- if (env->thumb)
+ if (env->thumb) {
offset = 2;
- else
+ } else {
offset = 4;
+ }
break;
case EXCP_SWI:
new_mode = ARM_CPU_MODE_SVC;
@@ -714,7 +717,8 @@ static void arm_cpu_do_interrupt_aarch32(CPUState *cs)
/* High vectors. When enabled, base address cannot be remapped. */
addr += 0xffff0000;
} else {
- /* ARM v7 architectures provide a vector base address register to remap
+ /*
+ * ARM v7 architectures provide a vector base address register to remap
* the interrupt vector table.
* This register is only followed in non-monitor mode, and is banked.
* Note: only bits 31:5 are valid.
@@ -1013,7 +1017,8 @@ void arm_log_exception(int idx)
}
}
-/* Handle a CPU exception for A and R profile CPUs.
+/*
+ * Handle a CPU exception for A and R profile CPUs.
* Do any appropriate logging, handle PSCI calls, and then hand off
* to the AArch64-entry or AArch32-entry function depending on the
* target exception level's register width.
diff --git a/target/arm/cpu32.c b/target/arm/cpu32.c
index 0ddb5627a7..08e9506509 100644
--- a/target/arm/cpu32.c
+++ b/target/arm/cpu32.c
@@ -92,7 +92,8 @@ static void cortex_a8_initfn(Object *obj)
}
static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
- /* power_control should be set to maximum latency. Again,
+ /*
+ * power_control should be set to maximum latency. Again,
* default to 0 and set by private hook
*/
{ .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
@@ -129,7 +130,8 @@ static void cortex_a9_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_NEON);
set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
set_feature(&cpu->env, ARM_FEATURE_EL3);
- /* Note that A9 supports the MP extensions even for
+ /*
+ * Note that A9 supports the MP extensions even for
* A9UP and single-core A9MP (which are both different
* and valid configurations; we don't model A9UP).
*/
@@ -166,7 +168,8 @@ static uint64_t a15_l2ctlr_read(CPUARMState *env, const
ARMCPRegInfo *ri)
{
MachineState *ms = MACHINE(qdev_get_machine());
- /* Linux wants the number of processors from here.
+ /*
+ * Linux wants the number of processors from here.
* Might as well set the interrupt-controller bit too.
*/
return ((ms->smp.cpus - 1) << 24) | (1 << 23);
@@ -213,7 +216,8 @@ static void cortex_a7_initfn(Object *obj)
cpu->isar.id_mmfr1 = 0x40000000;
cpu->isar.id_mmfr2 = 0x01240000;
cpu->isar.id_mmfr3 = 0x02102211;
- /* a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but
+ /*
+ * a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but
* table 4-41 gives 0x02101110, which includes the arm div insns.
*/
cpu->isar.id_isar0 = 0x02101110;
--
2.26.2
- [RFC v4 08/33] target/arm: cpu-mmu: fix comment style, (continued)
- [RFC v4 08/33] target/arm: cpu-mmu: fix comment style, Claudio Fontana, 2021/03/05
- [RFC v4 07/33] target/arm: move physical address translation to cpu-mmu, Claudio Fontana, 2021/03/05
- [RFC v4 09/33] target/arm: split cpregs from tcg/helper.c, Claudio Fontana, 2021/03/05
- [RFC v4 15/33] target/arm: add temporary stub for arm_rebuild_hflags, Claudio Fontana, 2021/03/05
- [RFC v4 13/33] target/arm: kvm: add stubs for some helpers, Claudio Fontana, 2021/03/05
- [RFC v4 18/33] target/arm: move sve_zcr_len_for_el to common_cpu, Claudio Fontana, 2021/03/05
- [RFC v4 12/33] target/arm: only perform TCG cpu and machine inits if TCG enabled, Claudio Fontana, 2021/03/05
- [RFC v4 16/33] target/arm: split vfp state setting from tcg helpers, Claudio Fontana, 2021/03/05
- [RFC v4 28/33] target/arm: move kvm-const.h, kvm.c, kvm64.c, kvm_arm.h to kvm/, Claudio Fontana, 2021/03/05
- [RFC v4 29/33] target/arm: cleanup cpu includes, Claudio Fontana, 2021/03/05
- [RFC v4 25/33] target/arm: cpu: fix style,
Claudio Fontana <=
- [RFC v4 14/33] target/arm: move cpsr_read, cpsr_write to cpu_common, Claudio Fontana, 2021/03/05
- [RFC v4 17/33] target/arm: move arm_mmu_idx* to cpu-mmu, Claudio Fontana, 2021/03/05
- [RFC v4 20/33] target/arm: move arm_cpu_list to common_cpu, Claudio Fontana, 2021/03/05
- [RFC v4 26/33] target/arm: wrap call to aarch64_sve_change_el in tcg_enabled(), Claudio Fontana, 2021/03/05
- [RFC v4 22/33] target/arm: split 32bit cpu models from cpu.c to cpu32.c, Claudio Fontana, 2021/03/05
- [RFC v4 21/33] target/arm: move aarch64_sync_32_to_64 (and vv) to cpu code, Claudio Fontana, 2021/03/05
- [RFC v4 23/33] target/arm: move sve_exception_el out of TCG helpers, Claudio Fontana, 2021/03/05
- [RFC v4 27/33] target/arm: remove kvm include file for PSCI and arm-powerctl, Claudio Fontana, 2021/03/05
- [RFC v4 30/33] target/arm: remove broad "else" statements when checking accels, Claudio Fontana, 2021/03/05