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[Bug 1918026] Re: RISCV64 32-bit AMOs incorrectly simulated
From: |
Richard Henderson |
Subject: |
[Bug 1918026] Re: RISCV64 32-bit AMOs incorrectly simulated |
Date: |
Sun, 07 Mar 2021 05:06:23 -0000 |
Flushing out the report to something that compiles,
the test case works for me using qemu 5.2.
** Attachment added: "z.c"
https://bugs.launchpad.net/qemu/+bug/1918026/+attachment/5474131/+files/z.c
** Changed in: qemu
Status: New => Fix Released
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https://bugs.launchpad.net/bugs/1918026
Title:
RISCV64 32-bit AMOs incorrectly simulated
Status in QEMU:
Fix Released
Bug description:
Version: qemu-riscv64 version 4.2.1 (Debian 1:4.2-3ubuntu6.14)
test:
amomaxu.w a0, a1, (a0)
ret
int32_t* value = -7;
EXPECT_EQ(-7, test(&value, -11));
EXPECT_EQ(-7, value); // FAIL, saw -11
EXPECT_EQ(-7, test(&value, -7));
EXPECT_EQ(-7, value); // FAIL, raw -11
EXPECT_EQ(-7, test(&value, -4));
EXPECT_EQ(-4, value);
test:
amomax.w a0, a1, (a0)
ret
int32_t* value = -7;
EXPECT_EQ(-7, test(&value, -11));
EXPECT_EQ(-7, value);
EXPECT_EQ(-7, test(&value, -7));
EXPECT_EQ(-7, value);
EXPECT_EQ(-7, test(&value, -4));
EXPECT_EQ(-4, value); // FAIL, saw -7
I suspect that trans_amo<op>_w should be using
tcg_gen_atomic_fetch_<op>_i32 instead of tcg_gen_atomic_fetch_<op>_tl.
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