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[PATCH RESEND 6/6] hw/mips/gt64xxx: Let the GT64120 manage the lower 512
From: |
Philippe Mathieu-Daudé |
Subject: |
[PATCH RESEND 6/6] hw/mips/gt64xxx: Let the GT64120 manage the lower 512MiB hole |
Date: |
Tue, 9 Mar 2021 15:26:30 +0100 |
Per the comment in the Malta board, the [0x0000.0000-0x2000.0000]
range is decoded by the GT64120, so move the "empty_slot" there.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/mips/gt64xxx_pci.c | 8 ++++++++
hw/mips/malta.c | 7 -------
2 files changed, 8 insertions(+), 7 deletions(-)
diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c
index 43349d6837d..a3926e5cb8a 100644
--- a/hw/mips/gt64xxx_pci.c
+++ b/hw/mips/gt64xxx_pci.c
@@ -29,6 +29,7 @@
#include "hw/mips/mips.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_host.h"
+#include "hw/misc/empty_slot.h"
#include "hw/southbridge/piix.h"
#include "migration/vmstate.h"
#include "hw/intc/i8259.h"
@@ -1206,6 +1207,13 @@ static void gt64120_realize(DeviceState *dev, Error
**errp)
memory_region_init_io(&s->ISD_mem, OBJECT(dev), &isd_mem_ops, s,
"gt64120-isd", 0x1000);
+
+ /*
+ * The whole address space decoded by the GT-64120A doesn't generate
+ * exception when accessing invalid memory. Create an empty slot to
+ * emulate this feature.
+ */
+ empty_slot_init("GT64120", 0, 0x20000000);
}
PCIBus *gt64120_register(qemu_irq *pic)
diff --git a/hw/mips/malta.c b/hw/mips/malta.c
index 9afc0b427bf..b2469f8ee78 100644
--- a/hw/mips/malta.c
+++ b/hw/mips/malta.c
@@ -56,7 +56,6 @@
#include "sysemu/runstate.h"
#include "qapi/error.h"
#include "qemu/error-report.h"
-#include "hw/misc/empty_slot.h"
#include "sysemu/kvm.h"
#include "hw/semihosting/semihost.h"
#include "hw/mips/cps.h"
@@ -1396,12 +1395,6 @@ void mips_malta_init(MachineState *machine)
/* Northbridge */
pci_bus = gt64120_register(s->i8259);
- /*
- * The whole address space decoded by the GT-64120A doesn't generate
- * exception when accessing invalid memory. Create an empty slot to
- * emulate this feature.
- */
- empty_slot_init("GT64120", 0, 0x20000000);
/* Southbridge */
dev = piix4_create(pci_bus, &isa_bus, &smbus);
--
2.26.2
- Re: [PATCH RESEND 1/6] hw/mips/gt64xxx: Initialize ISD I/O memory region in DeviceRealize(), (continued)
- [PATCH RESEND 2/6] hw/mips/gt64xxx: Simplify ISD MemoryRegion read/write handlers, Philippe Mathieu-Daudé, 2021/03/09
- [PATCH RESEND 3/6] hw/mips/gt64xxx: Fix typos in qemu_log_mask() formats, Philippe Mathieu-Daudé, 2021/03/09
- [PATCH RESEND 4/6] hw/mips/gt64xxx: Rename trace events related to interrupt registers, Philippe Mathieu-Daudé, 2021/03/09
- [PATCH RESEND 5/6] hw/mips/gt64xxx: Trace accesses to ISD registers, Philippe Mathieu-Daudé, 2021/03/09
- [PATCH RESEND 6/6] hw/mips/gt64xxx: Let the GT64120 manage the lower 512MiB hole,
Philippe Mathieu-Daudé <=
- Re: [PATCH RESEND 0/6] hw/mips/gt64120: Minor fixes, Philippe Mathieu-Daudé, 2021/03/11