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[PATCH 2/3] hw/gpio/avr_gpio.c: add tracing for read and writes
From: |
G S Niteesh Babu |
Subject: |
[PATCH 2/3] hw/gpio/avr_gpio.c: add tracing for read and writes |
Date: |
Thu, 11 Mar 2021 19:25:38 +0530 |
Added tracing for gpio read, write, and update output irq.
1) trace_avr_gpio_update_ouput_irq
2) trace_avr_gpio_read
3) trace_avr_gpio_write
Signed-off-by: G S Niteesh Babu <niteesh.gs@gmail.com>
---
hw/gpio/avr_gpio.c | 16 ++++++++++++----
hw/gpio/trace-events | 6 ++++++
2 files changed, 18 insertions(+), 4 deletions(-)
diff --git a/hw/gpio/avr_gpio.c b/hw/gpio/avr_gpio.c
index 8fc192dbcb..8498a99dd2 100644
--- a/hw/gpio/avr_gpio.c
+++ b/hw/gpio/avr_gpio.c
@@ -26,6 +26,7 @@
#include "hw/irq.h"
#include "hw/gpio/avr_gpio.h"
#include "hw/qdev-properties.h"
+#include "trace.h"
static void avr_gpio_reset(DeviceState *dev)
{
@@ -49,6 +50,7 @@ static void avr_gpio_write_port(AVRGPIOState *s, uint64_t
value)
if (cur_ddr_pin_val && (cur_port_pin_val != new_port_pin_val)) {
qemu_set_irq(s->out[pin], new_port_pin_val);
+ trace_avr_gpio_update_output_irq(pin, new_port_pin_val);
}
cur_port_val >>= 1u;
cur_ddr_val >>= 1u;
@@ -58,19 +60,25 @@ static void avr_gpio_write_port(AVRGPIOState *s, uint64_t
value)
}
static uint64_t avr_gpio_read(void *opaque, hwaddr offset, unsigned int size)
{
+ uint8_t val = 0;
AVRGPIOState *s = (AVRGPIOState *)opaque;
switch (offset) {
case GPIO_PIN:
- return s->reg.pin;
+ val = s->reg.pin;
+ break;
case GPIO_DDR:
- return s->reg.ddr;
+ val = s->reg.ddr;
+ break;
case GPIO_PORT:
- return s->reg.port;
+ val = s->reg.port;
+ break;
default:
g_assert_not_reached();
break;
}
- return 0;
+
+ trace_avr_gpio_read(offset, val);
+ return val;
}
static void avr_gpio_write(void *opaque, hwaddr offset, uint64_t value,
diff --git a/hw/gpio/trace-events b/hw/gpio/trace-events
index 46ab9323bd..a054def07c 100644
--- a/hw/gpio/trace-events
+++ b/hw/gpio/trace-events
@@ -18,3 +18,9 @@ sifive_gpio_read(uint64_t offset, uint64_t r) "offset 0x%"
PRIx64 " value 0x%" P
sifive_gpio_write(uint64_t offset, uint64_t value) "offset 0x%" PRIx64 " value
0x%" PRIx64
sifive_gpio_set(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64
sifive_gpio_update_output_irq(int64_t line, int64_t value) "line %" PRIi64 "
value %" PRIi64
+
+# avr_gpio.c
+avr_gpio_read(uint64_t offset, uint64_t r) "offset 0x%" PRIx64 " value 0x%"
PRIx64
+avr_gpio_write(uint64_t offset, uint64_t value) "offset 0x%" PRIx64 " value
0x%" PRIx64
+avr_gpio_set(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64
+avr_gpio_update_output_irq(int64_t line, int64_t value) "pin %" PRIi64 " value
%" PRIi64
--
2.17.1