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[PATCH v3 1/5] target/mips/tx79: Introduce LQ opcode (Load Quadword)
From: |
Philippe Mathieu-Daudé |
Subject: |
[PATCH v3 1/5] target/mips/tx79: Introduce LQ opcode (Load Quadword) |
Date: |
Fri, 12 Mar 2021 17:24:30 +0100 |
Introduce the LQ opcode (Load Quadword) and remove unreachable code.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210214175912.732946-26-f4bug@amsat.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/tx79.decode | 8 ++++++++
target/mips/translate.c | 16 ++--------------
target/mips/tx79_translate.c | 35 +++++++++++++++++++++++++++++++++++
3 files changed, 45 insertions(+), 14 deletions(-)
diff --git a/target/mips/tx79.decode b/target/mips/tx79.decode
index 0f748b53a64..f1f17470a00 100644
--- a/target/mips/tx79.decode
+++ b/target/mips/tx79.decode
@@ -13,6 +13,8 @@
&rtype rs rt rd sa
+&itype base rt offset
+
###########################################################################
# Named instruction formats. These are generally used to
# reduce the amount of duplication between instruction patterns.
@@ -22,6 +24,8 @@
@rs ...... rs:5 ..... .......... ...... &rtype rt=0 rd=0 sa=0
@rd ...... .......... rd:5 ..... ...... &rtype rs=0 rt=0 sa=0
+@ldst ...... base:5 rt:5 offset:16 &itype
+
###########################################################################
MFHI1 011100 0000000000 ..... 00000 010000 @rd
@@ -37,3 +41,7 @@ PCPYLD 011100 ..... ..... ..... 01110 001001
@rs_rt_rd
PCPYUD 011100 ..... ..... ..... 01110 101001 @rs_rt_rd
PCPYH 011100 00000 ..... ..... 11011 101001 @rt_rd
+
+# SPECIAL
+
+LQ 011110 ..... ..... ................ @ldst
diff --git a/target/mips/translate.c b/target/mips/translate.c
index c518bf3963b..c822083f031 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -1167,7 +1167,6 @@ enum {
enum {
MMI_OPC_CLASS_MMI = 0x1C << 26, /* Same as OPC_SPECIAL2 */
- MMI_OPC_LQ = 0x1E << 26, /* Same as OPC_MSA */
MMI_OPC_SQ = 0x1F << 26, /* Same as OPC_SPECIAL3 */
};
@@ -24429,11 +24428,6 @@ static void decode_mmi(CPUMIPSState *env, DisasContext
*ctx)
}
}
-static void gen_mmi_lq(CPUMIPSState *env, DisasContext *ctx)
-{
- gen_reserved_instruction(ctx); /* TODO: MMI_OPC_LQ */
-}
-
static void gen_mmi_sq(DisasContext *ctx, int base, int rt, int offset)
{
gen_reserved_instruction(ctx); /* TODO: MMI_OPC_SQ */
@@ -25332,14 +25326,8 @@ static bool decode_opc_legacy(CPUMIPSState *env,
DisasContext *ctx)
gen_compute_branch(ctx, op, 4, rs, rt, offset, 4);
}
break;
- case OPC_MDMX: /* MMI_OPC_LQ */
- if (ctx->insn_flags & INSN_R5900) {
-#if defined(TARGET_MIPS64)
- gen_mmi_lq(env, ctx);
-#endif
- } else {
- /* MDMX: Not implemented. */
- }
+ case OPC_MDMX:
+ /* MDMX: Not implemented. */
break;
case OPC_PCREL:
check_insn(ctx, ISA_MIPS_R6);
diff --git a/target/mips/tx79_translate.c b/target/mips/tx79_translate.c
index ad83774b977..b5a9eb3de76 100644
--- a/target/mips/tx79_translate.c
+++ b/target/mips/tx79_translate.c
@@ -177,6 +177,41 @@ static bool trans_MTLO1(DisasContext *ctx, arg_rtype *a)
* SQ rt, offset(base) Store Quadword
*/
+static bool trans_LQ(DisasContext *ctx, arg_itype *a)
+{
+ TCGv_i64 t0;
+ TCGv addr;
+
+ if (a->rt == 0) {
+ /* nop */
+ return true;
+ }
+
+ t0 = tcg_temp_new_i64();
+ addr = tcg_temp_new();
+
+ gen_base_offset_addr(ctx, addr, a->base, a->offset);
+ /*
+ * Clear least-significant four bits of the effective
+ * address, effectively creating an aligned address.
+ */
+ tcg_gen_andi_tl(addr, addr, ~0xf);
+
+ /* Lower half */
+ tcg_gen_qemu_ld_i64(t0, addr, ctx->mem_idx, MO_TEQ);
+ gen_store_gpr(t0, a->rt);
+
+ /* Upper half */
+ tcg_gen_addi_i64(addr, addr, 8);
+ tcg_gen_qemu_ld_i64(t0, addr, ctx->mem_idx, MO_TEQ);
+ gen_store_gpr_hi(t0, a->rt);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(addr);
+
+ return true;
+}
+
/*
* Multiply and Divide (19 instructions)
* -------------------------------------
--
2.26.2