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[PATCH v1 0/5] RISC-V: Convert the CSR access functions to use
From: |
Alistair Francis |
Subject: |
[PATCH v1 0/5] RISC-V: Convert the CSR access functions to use |
Date: |
Wed, 17 Mar 2021 13:39:44 -0400 |
Alistair Francis (5):
target/riscv: Convert the RISC-V exceptions to an enum
target/riscv: Use the RiscVException enum for CSR predicates
target/riscv: Fix 32-bit HS mode access permissions
target/riscv: Use the RiscVException enum for CSR operations
target/riscv: Use RiscVException enum for CSR access
target/riscv/cpu.h | 28 +-
target/riscv/cpu_bits.h | 44 +--
target/riscv/cpu.c | 2 +-
target/riscv/cpu_helper.c | 4 +-
target/riscv/csr.c | 753 ++++++++++++++++++++++----------------
target/riscv/gdbstub.c | 8 +-
target/riscv/op_helper.c | 18 +-
7 files changed, 499 insertions(+), 358 deletions(-)
--
2.30.1
- [PATCH v1 0/5] RISC-V: Convert the CSR access functions to use,
Alistair Francis <=
- [PATCH v1 1/5] target/riscv: Convert the RISC-V exceptions to an enum, Alistair Francis, 2021/03/17
- [PATCH v1 2/5] target/riscv: Use the RiscVException enum for CSR predicates, Alistair Francis, 2021/03/17
- [PATCH v1 3/5] target/riscv: Fix 32-bit HS mode access permissions, Alistair Francis, 2021/03/17
- [PATCH v1 4/5] target/riscv: Use the RiscVException enum for CSR operations, Alistair Francis, 2021/03/17
- [PATCH v1 5/5] target/riscv: Use RiscVException enum for CSR access, Alistair Francis, 2021/03/17