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[RFC v9 18/50] target/arm: move sve_zcr_len_for_el to common_cpu
From: |
Claudio Fontana |
Subject: |
[RFC v9 18/50] target/arm: move sve_zcr_len_for_el to common_cpu |
Date: |
Wed, 17 Mar 2021 19:29:41 +0100 |
it is required by arch-dump.c and cpu.c, so apparently
we need this for KVM too
Signed-off-by: Claudio Fontana <cfontana@suse.de>
---
target/arm/cpu-common.c | 43 +++++++++++++++++++++++++++++++++++++++++
target/arm/tcg/helper.c | 33 -------------------------------
2 files changed, 43 insertions(+), 33 deletions(-)
diff --git a/target/arm/cpu-common.c b/target/arm/cpu-common.c
index 694e5d73f3..540793e4c0 100644
--- a/target/arm/cpu-common.c
+++ b/target/arm/cpu-common.c
@@ -231,3 +231,46 @@ void cpsr_write(CPUARMState *env, uint32_t val, uint32_t
mask,
mask &= ~CACHED_CPSR_BITS;
env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
}
+
+/*
+ * these are AARCH64-only, but due to the chain of dependencies,
+ * between HELPER prototypes, hflags, cpreg definitions and functions in
+ * tcg/ etc, it becomes incredibly messy to add what should be here:
+ *
+ * #ifdef TARGET_AARCH64
+ */
+
+static uint32_t sve_zcr_get_valid_len(ARMCPU *cpu, uint32_t start_len)
+{
+ uint32_t end_len;
+
+ end_len = start_len &= 0xf;
+ if (!test_bit(start_len, cpu->sve_vq_map)) {
+ end_len = find_last_bit(cpu->sve_vq_map, start_len);
+ assert(end_len < start_len);
+ }
+ return end_len;
+}
+
+/*
+ * Given that SVE is enabled, return the vector length for EL.
+ */
+uint32_t sve_zcr_len_for_el(CPUARMState *env, int el)
+{
+ ARMCPU *cpu = env_archcpu(env);
+ uint32_t zcr_len = cpu->sve_max_vq - 1;
+
+ if (el <= 1) {
+ zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[1]);
+ }
+ if (el <= 2 && arm_feature(env, ARM_FEATURE_EL2)) {
+ zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[2]);
+ }
+ if (arm_feature(env, ARM_FEATURE_EL3)) {
+ zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[3]);
+ }
+
+ return sve_zcr_get_valid_len(cpu, zcr_len);
+}
+
+/* #endif TARGET_AARCH64 , see matching comment above */
diff --git a/target/arm/tcg/helper.c b/target/arm/tcg/helper.c
index beaf252ca5..ec0b812f96 100644
--- a/target/arm/tcg/helper.c
+++ b/target/arm/tcg/helper.c
@@ -390,39 +390,6 @@ int sve_exception_el(CPUARMState *env, int el)
return 0;
}
-static uint32_t sve_zcr_get_valid_len(ARMCPU *cpu, uint32_t start_len)
-{
- uint32_t end_len;
-
- end_len = start_len &= 0xf;
- if (!test_bit(start_len, cpu->sve_vq_map)) {
- end_len = find_last_bit(cpu->sve_vq_map, start_len);
- assert(end_len < start_len);
- }
- return end_len;
-}
-
-/*
- * Given that SVE is enabled, return the vector length for EL.
- */
-uint32_t sve_zcr_len_for_el(CPUARMState *env, int el)
-{
- ARMCPU *cpu = env_archcpu(env);
- uint32_t zcr_len = cpu->sve_max_vq - 1;
-
- if (el <= 1) {
- zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[1]);
- }
- if (el <= 2 && arm_feature(env, ARM_FEATURE_EL2)) {
- zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[2]);
- }
- if (arm_feature(env, ARM_FEATURE_EL3)) {
- zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[3]);
- }
-
- return sve_zcr_get_valid_len(cpu, zcr_len);
-}
-
void hw_watchpoint_update(ARMCPU *cpu, int n)
{
CPUARMState *env = &cpu->env;
--
2.26.2
- [RFC v9 06/50] target/arm: split off cpu-sysemu.c, (continued)
- [RFC v9 06/50] target/arm: split off cpu-sysemu.c, Claudio Fontana, 2021/03/17
- [RFC v9 11/50] target/arm: move cpu definitions to common cpu module, Claudio Fontana, 2021/03/17
- [RFC v9 16/50] target/arm: split vfp state setting from tcg helpers, Claudio Fontana, 2021/03/17
- [RFC v9 19/50] target/arm: move arm_sctlr away from tcg helpers, Claudio Fontana, 2021/03/17
- [RFC v9 08/50] target/arm: cpu-mmu: fix comment style, Claudio Fontana, 2021/03/17
- [RFC v9 15/50] target/arm: add temporary stub for arm_rebuild_hflags, Claudio Fontana, 2021/03/17
- [RFC v9 14/50] target/arm: move cpsr_read, cpsr_write to cpu_common, Claudio Fontana, 2021/03/17
- [RFC v9 17/50] target/arm: move arm_mmu_idx* to cpu-mmu, Claudio Fontana, 2021/03/17
- [RFC v9 20/50] target/arm: move arm_cpu_list to common_cpu, Claudio Fontana, 2021/03/17
- [RFC v9 13/50] target/arm: kvm: add stubs for some helpers, Claudio Fontana, 2021/03/17
- [RFC v9 18/50] target/arm: move sve_zcr_len_for_el to common_cpu,
Claudio Fontana <=
- [RFC v9 21/50] target/arm: move aarch64_sync_32_to_64 (and vv) to cpu code, Claudio Fontana, 2021/03/17
- [RFC v9 27/50] target/arm: remove kvm include file for PSCI and arm-powerctl, Claudio Fontana, 2021/03/17
- [RFC v9 32/50] tests: restrict TCG-only arm-cpu-features tests to TCG builds, Claudio Fontana, 2021/03/17
- [RFC v9 35/50] tests: do not run qom-test on all machines for ARM KVM-only, Claudio Fontana, 2021/03/17
- [RFC v9 38/50] target/arm: move kvm cpu properties setting to kvm-cpu, Claudio Fontana, 2021/03/17
- [RFC v9 43/50] target/arm: cpu-sve: new module, Claudio Fontana, 2021/03/17
- [RFC v9 26/50] target/arm: wrap call to aarch64_sve_change_el in tcg_enabled(), Claudio Fontana, 2021/03/17
- [RFC v9 23/50] target/arm: move sve_exception_el out of TCG helpers, Claudio Fontana, 2021/03/17
- [RFC v9 25/50] target/arm: cpu: fix style, Claudio Fontana, 2021/03/17