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[PATCH v2 0/4] Add support for Shakti SoC from IIT-M
From: |
Vijai Kumar K |
Subject: |
[PATCH v2 0/4] Add support for Shakti SoC from IIT-M |
Date: |
Sun, 21 Mar 2021 10:39:13 +0530 |
This series adds initial suppport for emulating shakti soc[1] running
on arty 100T.
Shakti SoC uses Shakti C class core[2] and Shakti Uart[3]
[1] https://gitlab.com/shaktiproject/cores/shakti-soc/-/blob/master/README.rst
[2] https://gitlab.com/shaktiproject/cores/c-class/-/blob/master/README.md
[3] https://gitlab.com/shaktiproject/uncore/devices/-/tree/master/uart_v2
Changes in v2:
- Moved CPU addition to a separate patch(P1)
- Use riscv_setup_rom_resetvec API to setup reset vector
- Dropped unused DPRINTF and unwanted break statements
- Fixed uart_can_receive logic
- Reused sifive_u_cpu_init routine for shakti
- Error out when an unsupported CPU is specified
- Addressed formatting changes pointed out in review
Vijai Kumar K (4):
target/riscv: Add Shakti C class CPU
riscv: Add initial support for Shakti C machine
hw/char: Add Shakti UART emulation
hw/riscv: Connect Shakti UART to Shakti platform
MAINTAINERS | 9 +
default-configs/devices/riscv64-softmmu.mak | 1 +
hw/char/meson.build | 1 +
hw/char/shakti_uart.c | 185 ++++++++++++++++++++
hw/char/trace-events | 4 +
hw/riscv/Kconfig | 10 ++
hw/riscv/meson.build | 1 +
hw/riscv/shakti_c.c | 179 +++++++++++++++++++
include/hw/char/shakti_uart.h | 74 ++++++++
include/hw/riscv/shakti_c.h | 76 ++++++++
target/riscv/cpu.c | 1 +
target/riscv/cpu.h | 1 +
12 files changed, 542 insertions(+)
create mode 100644 hw/char/shakti_uart.c
create mode 100644 hw/riscv/shakti_c.c
create mode 100644 include/hw/char/shakti_uart.h
create mode 100644 include/hw/riscv/shakti_c.h
--
2.25.1
- [PATCH v2 0/4] Add support for Shakti SoC from IIT-M,
Vijai Kumar K <=