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[PULL 5/7] hw/sd: sdhci: Correctly set the controller status for ADMA
From: |
Philippe Mathieu-Daudé |
Subject: |
[PULL 5/7] hw/sd: sdhci: Correctly set the controller status for ADMA |
Date: |
Mon, 22 Mar 2021 18:16:08 +0100 |
From: Bin Meng <bmeng.cn@gmail.com>
When an ADMA transfer is started, the codes forget to set the
controller status to indicate a transfer is in progress.
With this fix, the following 2 reproducers:
https://paste.debian.net/plain/1185136
https://paste.debian.net/plain/1185141
cannot be reproduced with the following QEMU command line:
$ qemu-system-x86_64 -nographic -machine accel=qtest -m 512M \
-nodefaults -device sdhci-pci,sd-spec-version=3 \
-drive if=sd,index=0,file=null-co://,format=raw,id=mydrive \
-device sd-card,drive=mydrive -qtest stdio
Cc: qemu-stable@nongnu.org
Fixes: CVE-2020-17380
Fixes: CVE-2020-25085
Fixes: CVE-2021-3409
Fixes: d7dfca0807a0 ("hw/sdhci: introduce standard SD host controller")
Reported-by: Alexander Bulekov <alxndr@bu.edu>
Reported-by: Cornelius Aschermann (Ruhr-Universität Bochum)
Reported-by: Sergej Schumilo (Ruhr-Universität Bochum)
Reported-by: Simon Wörner (Ruhr-Universität Bochum)
Buglink: https://bugs.launchpad.net/qemu/+bug/1892960
Buglink: https://bugs.launchpad.net/qemu/+bug/1909418
Buglink: https://bugzilla.redhat.com/show_bug.cgi?id=1928146
Tested-by: Alexander Bulekov <alxndr@bu.edu>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Message-Id: <20210303122639.20004-4-bmeng.cn@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/sd/sdhci.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
index 3feb6c3a1fe..7a2003b28b3 100644
--- a/hw/sd/sdhci.c
+++ b/hw/sd/sdhci.c
@@ -768,7 +768,9 @@ static void sdhci_do_adma(SDHCIState *s)
switch (dscr.attr & SDHC_ADMA_ATTR_ACT_MASK) {
case SDHC_ADMA_ATTR_ACT_TRAN: /* data transfer */
+ s->prnsts |= SDHC_DATA_INHIBIT | SDHC_DAT_LINE_ACTIVE;
if (s->trnmod & SDHC_TRNS_READ) {
+ s->prnsts |= SDHC_DOING_READ;
while (length) {
if (s->data_count == 0) {
sdbus_read_data(&s->sdbus, s->fifo_buffer, block_size);
@@ -796,6 +798,7 @@ static void sdhci_do_adma(SDHCIState *s)
}
}
} else {
+ s->prnsts |= SDHC_DOING_WRITE;
while (length) {
begin = s->data_count;
if ((length + begin) < block_size) {
--
2.26.2
- [PULL 0/7] SD/MMC patches for 2021-03-21, Philippe Mathieu-Daudé, 2021/03/22
- [PULL 1/7] hw/sd: sd: Fix build error when DEBUG_SD is on, Philippe Mathieu-Daudé, 2021/03/22
- [PULL 2/7] hw/sd: sd: Actually perform the erase operation, Philippe Mathieu-Daudé, 2021/03/22
- [PULL 3/7] hw/sd: sdhci: Don't transfer any data when command time out, Philippe Mathieu-Daudé, 2021/03/22
- [PULL 4/7] hw/sd: sdhci: Don't write to SDHC_SYSAD register when transfer is in progress, Philippe Mathieu-Daudé, 2021/03/22
- [PULL 5/7] hw/sd: sdhci: Correctly set the controller status for ADMA,
Philippe Mathieu-Daudé <=
- [PULL 6/7] hw/sd: sdhci: Limit block size only when SDHC_BLKSIZE register is writable, Philippe Mathieu-Daudé, 2021/03/22
- [PULL 7/7] hw/sd: sdhci: Reset the data pointer of s->fifo_buffer[] when a different block size is programmed, Philippe Mathieu-Daudé, 2021/03/22
- Re: [PULL 0/7] SD/MMC patches for 2021-03-21, Peter Maydell, 2021/03/23