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[RFC v12 28/65] target/arm: fixup sve_exception_el code style before mov
From: |
Claudio Fontana |
Subject: |
[RFC v12 28/65] target/arm: fixup sve_exception_el code style before move |
Date: |
Fri, 26 Mar 2021 20:36:24 +0100 |
before moving over sve_exception_el from the helper code,
cleanup the style.
Signed-off-by: Claudio Fontana <cfontana@suse.de>
---
target/arm/tcg/helper.c | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/target/arm/tcg/helper.c b/target/arm/tcg/helper.c
index 5ec8f9c005..e4f18bcaa7 100644
--- a/target/arm/tcg/helper.c
+++ b/target/arm/tcg/helper.c
@@ -261,7 +261,8 @@ static int arm_gdb_set_svereg(CPUARMState *env, uint8_t
*buf, int reg)
}
#endif /* TARGET_AARCH64 */
-/* Return the exception level to which exceptions should be taken
+/*
+ * Return the exception level to which exceptions should be taken
* via SVEAccessTrap. If an exception should be routed through
* AArch64.AdvSIMDFPAccessTrap, return 0; fp_exception_el should
* take care of raising that exception.
@@ -275,7 +276,8 @@ int sve_exception_el(CPUARMState *env, int el)
if (el <= 1 && (hcr_el2 & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) {
bool disabled = false;
- /* The CPACR.ZEN controls traps to EL1:
+ /*
+ * The CPACR.ZEN controls traps to EL1:
* 0, 2 : trap EL0 and EL1 accesses
* 1 : trap only EL0 accesses
* 3 : trap no accesses
@@ -301,7 +303,8 @@ int sve_exception_el(CPUARMState *env, int el)
}
}
- /* CPTR_EL2. Since TZ and TFP are positive,
+ /*
+ * CPTR_EL2. Since TZ and TFP are positive,
* they will be zero when EL2 is not present.
*/
if (el <= 2 && arm_is_el2_enabled(env)) {
--
2.26.2
- [RFC v12 16/65] target/arm: only perform TCG cpu and machine inits if TCG enabled, (continued)
- [RFC v12 16/65] target/arm: only perform TCG cpu and machine inits if TCG enabled, Claudio Fontana, 2021/03/26
- [RFC v12 20/65] target/arm: move arm_hcr_el2_eff from tcg/ to common_cpu, Claudio Fontana, 2021/03/26
- [RFC v12 14/65] target/arm: split cpregs from tcg/helper.c, Claudio Fontana, 2021/03/26
- [RFC v12 21/65] target/arm: split vfp state setting from tcg helpers, Claudio Fontana, 2021/03/26
- [RFC v12 22/65] target/arm: move arm_mmu_idx* to cpu-mmu, Claudio Fontana, 2021/03/26
- [RFC v12 24/65] target/arm: move arm_sctlr away from tcg helpers, Claudio Fontana, 2021/03/26
- [RFC v12 28/65] target/arm: fixup sve_exception_el code style before move,
Claudio Fontana <=
- [RFC v12 23/65] target/arm: move sve_zcr_len_for_el to common_cpu, Claudio Fontana, 2021/03/26
- [RFC v12 25/65] target/arm: move arm_cpu_list to common_cpu, Claudio Fontana, 2021/03/26
- [RFC v12 30/65] target/arm: fix style of arm_cpu_do_interrupt functions before move, Claudio Fontana, 2021/03/26
- [RFC v12 26/65] target/arm: move aarch64_sync_32_to_64 (and vv) to cpu code, Claudio Fontana, 2021/03/26
- [RFC v12 29/65] target/arm: move sve_exception_el out of TCG helpers, Claudio Fontana, 2021/03/26
- [RFC v12 31/65] target/arm: move exception code out of tcg/helper.c, Claudio Fontana, 2021/03/26
- [RFC v12 32/65] target/arm: move TCGCPUOps to tcg/tcg-cpu.c, Claudio Fontana, 2021/03/26