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[PULL 5/5] hw/timer/renesas_tmr: Add default-case asserts in read_tcnt()
From: |
Peter Maydell |
Subject: |
[PULL 5/5] hw/timer/renesas_tmr: Add default-case asserts in read_tcnt() |
Date: |
Tue, 30 Mar 2021 14:25:55 +0100 |
In commit 81b3ddaf8772ec we fixed a use of uninitialized data
in read_tcnt(). However this change wasn't enough to placate
Coverity, which is not smart enough to see that if we read a
2 bit field and then handle cases 0, 1, 2 and 3 then there cannot
be a flow of execution through the switch default. Add explicit
default cases which assert that they can't be reached, which
should help silence Coverity.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210319162458.13760-1-peter.maydell@linaro.org
---
hw/timer/renesas_tmr.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/hw/timer/renesas_tmr.c b/hw/timer/renesas_tmr.c
index eed39917fec..d96002e1ee6 100644
--- a/hw/timer/renesas_tmr.c
+++ b/hw/timer/renesas_tmr.c
@@ -146,6 +146,8 @@ static uint16_t read_tcnt(RTMRState *tmr, unsigned size,
int ch)
case CSS_CASCADING:
tcnt[1] = tmr->tcnt[1];
break;
+ default:
+ g_assert_not_reached();
}
switch (FIELD_EX8(tmr->tccr[0], TCCR, CSS)) {
case CSS_INTERNAL:
@@ -159,6 +161,8 @@ static uint16_t read_tcnt(RTMRState *tmr, unsigned size,
int ch)
case CSS_EXTERNAL: /* QEMU doesn't implement this */
tcnt[0] = tmr->tcnt[0];
break;
+ default:
+ g_assert_not_reached();
}
} else {
tcnt[0] = tmr->tcnt[0];
--
2.20.1
- [PULL 0/5] target-arm queue, Peter Maydell, 2021/03/30
- [PULL 2/5] hw/display/xlnx_dp: Free FIFOs adding xlnx_dp_finalize(), Peter Maydell, 2021/03/30
- [PULL 4/5] target/arm: Make number of counters in PMCR follow the CPU, Peter Maydell, 2021/03/30
- [PULL 1/5] net/npcm7xx_emc.c: Fix handling of receiving packets when RSDR not set, Peter Maydell, 2021/03/30
- [PULL 5/5] hw/timer/renesas_tmr: Add default-case asserts in read_tcnt(),
Peter Maydell <=
- [PULL 3/5] hw/arm/smmuv3: Drop unused CDM_VALID() and is_cd_valid(), Peter Maydell, 2021/03/30
- Re: [PULL 0/5] target-arm queue, Peter Maydell, 2021/03/30