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Re: [PATCH 3/8] hw/riscv: Support the official CLINT DT bindings
From: |
Alistair Francis |
Subject: |
Re: [PATCH 3/8] hw/riscv: Support the official CLINT DT bindings |
Date: |
Wed, 31 Mar 2021 11:42:44 -0400 |
On Mon, Mar 29, 2021 at 1:15 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> Linux kernel commit a2770b57d083 ("dt-bindings: timer: Add CLINT bindings")
> adds the official DT bindings for CLINT, which uses "sifive,clint0"
> as the compatible string. "riscv,clint0" is now legacy and has to
> be kept for backward compatibility of legacy systems.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
>
> hw/riscv/sifive_u.c | 4 +++-
> hw/riscv/spike.c | 4 +++-
> hw/riscv/virt.c | 4 +++-
> 3 files changed, 9 insertions(+), 3 deletions(-)
>
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index f06b3b2e64..7f696ebc12 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -97,6 +97,7 @@ static void create_fdt(SiFiveUState *s, const MemMapEntry
> *memmap,
> uint32_t *cells;
> char *nodename;
> const char *ethclk_names[2] = { "pclk", "hclk" };
> + const char *clint_compat[2] = { "sifive,clint0", "riscv,clint0" };
> uint32_t plic_phandle, prci_phandle, gpio_phandle, phandle = 1;
> uint32_t hfclk_phandle, rtcclk_phandle, phy_phandle;
>
> @@ -210,7 +211,8 @@ static void create_fdt(SiFiveUState *s, const MemMapEntry
> *memmap,
> nodename = g_strdup_printf("/soc/clint@%lx",
> (long)memmap[SIFIVE_U_DEV_CLINT].base);
> qemu_fdt_add_subnode(fdt, nodename);
> - qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0");
> + qemu_fdt_setprop_string_array(fdt, nodename, "compatible",
> + (char **)&clint_compat, ARRAY_SIZE(clint_compat));
> qemu_fdt_setprop_cells(fdt, nodename, "reg",
> 0x0, memmap[SIFIVE_U_DEV_CLINT].base,
> 0x0, memmap[SIFIVE_U_DEV_CLINT].size);
> diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
> index ec7cb2f707..cc33061f23 100644
> --- a/hw/riscv/spike.c
> +++ b/hw/riscv/spike.c
> @@ -60,6 +60,7 @@ static void create_fdt(SpikeState *s, const MemMapEntry
> *memmap,
> uint32_t cpu_phandle, intc_phandle, phandle = 1;
> char *name, *mem_name, *clint_name, *clust_name;
> char *core_name, *cpu_name, *intc_name;
> + const char *clint_compat[2] = { "sifive,clint0", "riscv,clint0" };
>
> fdt = s->fdt = create_device_tree(&s->fdt_size);
> if (!fdt) {
> @@ -153,7 +154,8 @@ static void create_fdt(SpikeState *s, const MemMapEntry
> *memmap,
> (memmap[SPIKE_CLINT].size * socket);
> clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr);
> qemu_fdt_add_subnode(fdt, clint_name);
> - qemu_fdt_setprop_string(fdt, clint_name, "compatible",
> "riscv,clint0");
> + qemu_fdt_setprop_string_array(fdt, clint_name, "compatible",
> + (char **)&clint_compat, ARRAY_SIZE(clint_compat));
> qemu_fdt_setprop_cells(fdt, clint_name, "reg",
> 0x0, clint_addr, 0x0, memmap[SPIKE_CLINT].size);
> qemu_fdt_setprop(fdt, clint_name, "interrupts-extended",
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> index 5d0c1e5903..5b4fac015d 100644
> --- a/hw/riscv/virt.c
> +++ b/hw/riscv/virt.c
> @@ -193,6 +193,7 @@ static void create_fdt(RISCVVirtState *s, const
> MemMapEntry *memmap,
> uint32_t plic_pcie_phandle = 1, plic_virtio_phandle = 1;
> char *mem_name, *cpu_name, *core_name, *intc_name;
> char *name, *clint_name, *plic_name, *clust_name;
> + const char *clint_compat[2] = { "sifive,clint0", "riscv,clint0" };
> hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2;
> hwaddr flashbase = virt_memmap[VIRT_FLASH].base;
>
> @@ -300,7 +301,8 @@ static void create_fdt(RISCVVirtState *s, const
> MemMapEntry *memmap,
> (memmap[VIRT_CLINT].size * socket);
> clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr);
> qemu_fdt_add_subnode(fdt, clint_name);
> - qemu_fdt_setprop_string(fdt, clint_name, "compatible",
> "riscv,clint0");
> + qemu_fdt_setprop_string_array(fdt, clint_name, "compatible",
> + (char **)&clint_compat, ARRAY_SIZE(clint_compat));
> qemu_fdt_setprop_cells(fdt, clint_name, "reg",
> 0x0, clint_addr, 0x0, memmap[VIRT_CLINT].size);
> qemu_fdt_setprop(fdt, clint_name, "interrupts-extended",
> --
> 2.25.1
>
>
- [PATCH 1/8] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper, Bin Meng, 2021/03/29
- [PATCH 2/8] hw/riscv: virt: Switch to use qemu_fdt_setprop_string_array() helper, Bin Meng, 2021/03/29
- [PATCH 3/8] hw/riscv: Support the official CLINT DT bindings, Bin Meng, 2021/03/29
- Re: [PATCH 3/8] hw/riscv: Support the official CLINT DT bindings,
Alistair Francis <=
- [PATCH 4/8] hw/riscv: Support the official PLIC DT bindings, Bin Meng, 2021/03/29
- [PATCH 6/8] docs/system/riscv: sifive_u: Document '-dtb' usage, Bin Meng, 2021/03/29
- [PATCH 5/8] docs/system/riscv: Correct the indentation level of supported devices, Bin Meng, 2021/03/29
- [PATCH 7/8] hw/riscv: Use macros for BIOS image names, Bin Meng, 2021/03/29
- [PATCH 8/8] hw/riscv: microchip_pfsoc: Support direct kernel boot, Bin Meng, 2021/03/29