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[PATCH v2 03/27] target/riscv: adding upper 64 bits for misa
From: |
Frédéric Pétrot |
Subject: |
[PATCH v2 03/27] target/riscv: adding upper 64 bits for misa |
Date: |
Wed, 6 Oct 2021 23:28:09 +0200 |
Addition of misah, upper part of misa in the 128-bit extension.
This is required for the is_64bit and is_128bit macros that we
introduce in addition to the existing is_32bit one to know which
register size the processor uses.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
---
target/riscv/cpu.h | 11 +++++++++++
target/riscv/cpu.c | 2 ++
target/riscv/translate.c | 21 ++++++++++++++++++++-
3 files changed, 33 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 5896aca346..0c41b60b25 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -37,6 +37,7 @@
#define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any")
#define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32")
#define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64")
+#define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("rv128")
#define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex")
#define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c")
#define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31")
@@ -49,10 +50,16 @@
# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32
#elif defined(TARGET_RISCV64)
# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64
+#else
+# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE128
#endif
+/* Mask for the MXLEN flag in the misa CSR */
+#define MXLEN_MASK ((target_ulong)3 << (TARGET_LONG_BITS - 2))
#define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2))
#define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2))
+/* To be used on misah, the upper part of misa */
+#define RV128 ((target_ulong)3 << (TARGET_LONG_BITS - 2))
#define RV(x) ((target_ulong)1 << (x - 'A'))
@@ -187,6 +194,10 @@ struct CPURISCVState {
target_ulong hgatp;
uint64_t htimedelta;
+ /* Upper 64-bits of 128-bit misa CSR */
+ uint64_t misah;
+ uint64_t misah_mask;
+
/* Virtual CSRs */
/*
* For RV32 this is 32-bit vsstatus and 32-bit vsstatush.
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 7c626d89cd..02417be926 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -154,8 +154,10 @@ static void riscv_any_cpu_init(Object *obj)
CPURISCVState *env = &RISCV_CPU(obj)->env;
#if defined(TARGET_RISCV32)
set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVU);
+ set_misah(env, 0);
#elif defined(TARGET_RISCV64)
set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVU);
+ set_misah(env, 0);
#endif
set_priv_version(env, PRIV_VERSION_1_11_0);
}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 74b33fa3c9..c04430805e 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -56,6 +56,7 @@ typedef struct DisasContext {
target_ulong pc_succ_insn;
target_ulong priv_ver;
target_ulong misa;
+ uint64_t misah;
uint32_t opcode;
uint32_t mstatus_fs;
uint32_t mem_idx;
@@ -90,13 +91,30 @@ static inline bool has_ext(DisasContext *ctx, uint32_t ext)
#ifdef TARGET_RISCV32
# define is_32bit(ctx) true
+# define is_64bit(ctx) false
+# define is_128bit(ctx) false
#elif defined(CONFIG_USER_ONLY)
# define is_32bit(ctx) false
+# define is_64_bit(ctx) true
+# define is_128_bit(ctx) false
#else
static inline bool is_32bit(DisasContext *ctx)
{
- return (ctx->misa & RV32) == RV32;
+ return (ctx->misa & MXLEN_MASK) == RV32;
}
+
+static inline bool is_64bit(DisasContext *ctx)
+{
+ return (ctx->misa & MXLEN_MASK) == RV64;
+}
+#if !defined(TARGET_RISCV64)
+static inline bool is_128bit(DisasContext *ctx)
+{
+ return (ctx->misah & MXLEN_MASK) == RV128;
+}
+#else
+# define is_128bit(ctx) false
+#endif
#endif
/* The word size for this operation. */
@@ -530,6 +548,7 @@ static void riscv_tr_init_disas_context(DisasContextBase
*dcbase, CPUState *cs)
ctx->virt_enabled = false;
#endif
ctx->misa = env->misa;
+ ctx->misah = env->misah;
ctx->frm = -1; /* unknown rounding mode */
ctx->ext_ifencei = cpu->cfg.ext_ifencei;
ctx->vlen = cpu->cfg.vlen;
--
2.33.0
- [PATCH v2 00/27] Adding partial support for 128-bit riscv target, Frédéric Pétrot, 2021/10/06
- [PATCH v2 03/27] target/riscv: adding upper 64 bits for misa,
Frédéric Pétrot <=
- [PATCH v2 01/27] memory: add a few defines for octo (128-bit) values, Frédéric Pétrot, 2021/10/06
- [PATCH v2 05/27] target/riscv: additional macros to check instruction support, Frédéric Pétrot, 2021/10/06
- [PATCH v2 10/27] target/riscv: adding accessors to the registers upper part, Frédéric Pétrot, 2021/10/06
- [PATCH v2 08/27] target/riscv: refactoring calls to gen_shift, Frédéric Pétrot, 2021/10/06
- [PATCH v2 04/27] target/riscv: array for the 64 upper bits of 128-bit registers, Frédéric Pétrot, 2021/10/06
- [PATCH v2 02/27] Int128.h: addition of a few 128-bit operations, Frédéric Pétrot, 2021/10/06
- [PATCH v2 09/27] target/riscv: setup everything so that riscv128-softmmu compiles, Frédéric Pétrot, 2021/10/06
- [PATCH v2 06/27] target/riscv: separation of bitwise logic and aritmetic helpers, Frédéric Pétrot, 2021/10/06
- [PATCH v2 07/27] target/riscv: refactoring calls to gen_arith, Frédéric Pétrot, 2021/10/06