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[PATCH 11/15] hw/nvme: Calculate BAR atributes in a function
From: |
Lukasz Maniak |
Subject: |
[PATCH 11/15] hw/nvme: Calculate BAR atributes in a function |
Date: |
Thu, 7 Oct 2021 18:24:02 +0200 |
From: Łukasz Gieryk <lukasz.gieryk@linux.intel.com>
An Nvme device with SR-IOV capability calculates the BAR size
differently for PF and VF, so it makes sense to extract the common code
to a separate function.
Also: it seems the n->reg_size parameter unnecessarily splits the BAR
size calculation in two phases; removed to simplify the code.
Signed-off-by: Łukasz Gieryk <lukasz.gieryk@linux.intel.com>
---
hw/nvme/ctrl.c | 52 +++++++++++++++++++++++++++++++++-----------------
hw/nvme/nvme.h | 1 -
2 files changed, 35 insertions(+), 18 deletions(-)
diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c
index 5d9166d66f..425fbf2c73 100644
--- a/hw/nvme/ctrl.c
+++ b/hw/nvme/ctrl.c
@@ -6339,10 +6339,6 @@ static void nvme_init_state(NvmeCtrl *n)
n->max_msix_qsize = n->params.msix_qsize;
n->conf_msix_qsize = n->max_msix_qsize;
-
- /* add one to max_ioqpairs to account for the admin queue pair */
- n->reg_size = pow2ceil(sizeof(NvmeBar) +
- 2 * (n->params.max_ioqpairs + 1) * NVME_DB_SIZE);
n->sq = g_new0(NvmeSQueue *, n->max_ioqpairs + 1);
n->cq = g_new0(NvmeCQueue *, n->max_ioqpairs + 1);
n->temperature = NVME_TEMPERATURE;
@@ -6401,6 +6397,36 @@ static void nvme_init_pmr(NvmeCtrl *n, PCIDevice
*pci_dev)
memory_region_set_enabled(&n->pmr.dev->mr, false);
}
+static uint64_t nvme_bar_size(unsigned total_queues, unsigned total_irqs,
+ unsigned *msix_table_offset,
+ unsigned *msix_pba_offset)
+{
+ uint64_t bar_size, msix_table_size, msix_pba_size;
+
+ bar_size = sizeof(NvmeBar);
+ bar_size += 2 * total_queues * NVME_DB_SIZE;
+ bar_size = pow2ceil(bar_size);
+ bar_size = QEMU_ALIGN_UP(bar_size, 4 * KiB);
+
+ if (msix_table_offset) {
+ *msix_table_offset = bar_size;
+ }
+
+ msix_table_size = PCI_MSIX_ENTRY_SIZE * total_irqs;
+ bar_size += msix_table_size;
+ bar_size = QEMU_ALIGN_UP(bar_size, 4 * KiB);
+
+ if (msix_pba_offset) {
+ *msix_pba_offset = bar_size;
+ }
+
+ msix_pba_size = QEMU_ALIGN_UP(total_irqs, 64) / 8;
+ bar_size += msix_pba_size;
+
+ bar_size = pow2ceil(bar_size);
+ return bar_size;
+}
+
static void nvme_update_vfs(PCIDevice *pci_dev, uint16_t prev_num_vfs,
uint16_t num_vfs)
{
@@ -6461,7 +6487,7 @@ static int nvme_add_pm_capability(PCIDevice *pci_dev,
uint8_t offset)
static int nvme_init_pci(NvmeCtrl *n, PCIDevice *pci_dev, Error **errp)
{
uint8_t *pci_conf = pci_dev->config;
- uint64_t bar_size, msix_table_size, msix_pba_size;
+ uint64_t bar_size;
unsigned msix_table_offset, msix_pba_offset;
int ret;
@@ -6486,21 +6512,13 @@ static int nvme_init_pci(NvmeCtrl *n, PCIDevice
*pci_dev, Error **errp)
pcie_ari_init(pci_dev, 0x100, 1);
}
- bar_size = QEMU_ALIGN_UP(n->reg_size, 4 * KiB);
- msix_table_offset = bar_size;
- msix_table_size = PCI_MSIX_ENTRY_SIZE * n->params.msix_qsize;
-
- bar_size += msix_table_size;
- bar_size = QEMU_ALIGN_UP(bar_size, 4 * KiB);
- msix_pba_offset = bar_size;
- msix_pba_size = QEMU_ALIGN_UP(n->params.msix_qsize, 64) / 8;
-
- bar_size += msix_pba_size;
- bar_size = pow2ceil(bar_size);
+ /* add one to max_ioqpairs to account for the admin queue pair */
+ bar_size = nvme_bar_size(n->max_ioqpairs + 1, n->max_msix_qsize,
+ &msix_table_offset, &msix_pba_offset);
memory_region_init(&n->bar0, OBJECT(n), "nvme-bar0", bar_size);
memory_region_init_io(&n->iomem, OBJECT(n), &nvme_mmio_ops, n, "nvme",
- n->reg_size);
+ msix_table_offset);
memory_region_add_subregion(&n->bar0, 0, &n->iomem);
if (pci_is_vf(pci_dev)) {
diff --git a/hw/nvme/nvme.h b/hw/nvme/nvme.h
index 65383e495c..a8eded4713 100644
--- a/hw/nvme/nvme.h
+++ b/hw/nvme/nvme.h
@@ -410,7 +410,6 @@ typedef struct NvmeCtrl {
uint16_t max_prp_ents;
uint16_t cqe_size;
uint16_t sqe_size;
- uint32_t reg_size;
uint32_t max_q_ents;
uint8_t outstanding_aers;
uint32_t irq_status;
--
2.25.1
- [PATCH 00/15] hw/nvme: SR-IOV with Virtualization Enhancements, Lukasz Maniak, 2021/10/07
- [PATCH 02/15] pcie: Add support for Single Root I/O Virtualization (SR/IOV), Lukasz Maniak, 2021/10/07
- [PATCH 12/15] hw/nvme: Initialize capability structures for primary/secondary controllers, Lukasz Maniak, 2021/10/07
- [PATCH 13/15] pcie: Add helpers to the SR/IOV API, Lukasz Maniak, 2021/10/07
- [PATCH 15/15] docs: Add documentation for SR-IOV and Virtualization Enhancements, Lukasz Maniak, 2021/10/07
- [PATCH 06/15] hw/nvme: Add support for Primary Controller Capabilities, Lukasz Maniak, 2021/10/07
- [PATCH 07/15] hw/nvme: Add support for Secondary Controller List, Lukasz Maniak, 2021/10/07
- [PATCH 09/15] hw/nvme: Implement the Function Level Reset, Lukasz Maniak, 2021/10/07
- [PATCH 11/15] hw/nvme: Calculate BAR atributes in a function,
Lukasz Maniak <=
- [PATCH 01/15] pcie: Set default and supported MaxReadReq to 512, Lukasz Maniak, 2021/10/07
- [PATCH 03/15] pcie: Add some SR/IOV API documentation in docs/pcie_sriov.txt, Lukasz Maniak, 2021/10/07
- [PATCH 14/15] hw/nvme: Add support for the Virtualization Management command, Lukasz Maniak, 2021/10/07
- [PATCH 04/15] pcie: Add callback preceding SR-IOV VFs update, Lukasz Maniak, 2021/10/07