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[PATCH v4 48/48] tests/tcg/multiarch: Add sigbus.c
From: |
Richard Henderson |
Subject: |
[PATCH v4 48/48] tests/tcg/multiarch: Add sigbus.c |
Date: |
Tue, 12 Oct 2021 19:46:07 -0700 |
A mostly generic test for unaligned access raising SIGBUS.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tests/tcg/multiarch/sigbus.c | 68 ++++++++++++++++++++++++++++++++++++
1 file changed, 68 insertions(+)
create mode 100644 tests/tcg/multiarch/sigbus.c
diff --git a/tests/tcg/multiarch/sigbus.c b/tests/tcg/multiarch/sigbus.c
new file mode 100644
index 0000000000..8134c5fd56
--- /dev/null
+++ b/tests/tcg/multiarch/sigbus.c
@@ -0,0 +1,68 @@
+#define _GNU_SOURCE 1
+
+#include <assert.h>
+#include <stdlib.h>
+#include <signal.h>
+#include <endian.h>
+
+
+unsigned long long x = 0x8877665544332211ull;
+void * volatile p = (void *)&x + 1;
+
+void sigbus(int sig, siginfo_t *info, void *uc)
+{
+ assert(sig == SIGBUS);
+ assert(info->si_signo == SIGBUS);
+#ifdef BUS_ADRALN
+ assert(info->si_code == BUS_ADRALN);
+#endif
+ assert(info->si_addr == p);
+ exit(EXIT_SUCCESS);
+}
+
+int main()
+{
+ struct sigaction sa = {
+ .sa_sigaction = sigbus,
+ .sa_flags = SA_SIGINFO
+ };
+ int allow_fail = 0;
+ int tmp;
+
+ tmp = sigaction(SIGBUS, &sa, NULL);
+ assert(tmp == 0);
+
+ /*
+ * Select an operation that's likely to enforce alignment.
+ * On many guests that support unaligned accesses by default,
+ * this is often an atomic operation.
+ */
+#if defined(__aarch64__)
+ asm volatile("ldxr %w0,[%1]" : "=r"(tmp) : "r"(p) : "memory");
+#elif defined(__alpha__)
+ asm volatile("ldl_l %0,0(%1)" : "=r"(tmp) : "r"(p) : "memory");
+#elif defined(__arm__)
+ asm volatile("ldrex %0,[%1]" : "=r"(tmp) : "r"(p) : "memory");
+#elif defined(__powerpc__)
+ asm volatile("lwarx %0,0,%1" : "=r"(tmp) : "r"(p) : "memory");
+#elif defined(__riscv_atomic)
+ asm volatile("lr.w %0,(%1)" : "=r"(tmp) : "r"(p) : "memory");
+#else
+ /* No insn known to fault unaligned -- try for a straight load. */
+ allow_fail = 1;
+ tmp = *(volatile int *)p;
+#endif
+
+ assert(allow_fail);
+
+ /*
+ * We didn't see a signal.
+ * We might as well validate the unaligned load worked.
+ */
+ if (BYTE_ORDER == LITTLE_ENDIAN) {
+ assert(tmp == 0x55443322);
+ } else {
+ assert(tmp == 0x77665544);
+ }
+ return EXIT_SUCCESS;
+}
--
2.25.1
- [PATCH v4 33/48] Revert "cpu: Move cpu_common_props to hw/core/cpu.c", (continued)
- [PATCH v4 33/48] Revert "cpu: Move cpu_common_props to hw/core/cpu.c", Richard Henderson, 2021/10/12
- [PATCH v4 38/48] target/hppa: Implement prctl_unalign_sigbus, Richard Henderson, 2021/10/12
- [PATCH v4 40/48] linux-user/signal: Handle BUS_ADRALN in host_signal_handler, Richard Henderson, 2021/10/12
- [PATCH v4 41/48] tcg: Canonicalize alignment flags in MemOp, Richard Henderson, 2021/10/12
- [PATCH v4 43/48] tcg/aarch64: Support raising sigbus for user-only, Richard Henderson, 2021/10/12
- [PATCH v4 42/48] tcg/i386: Support raising sigbus for user-only, Richard Henderson, 2021/10/12
- [PATCH v4 44/48] tcg/ppc: Support raising sigbus for user-only, Richard Henderson, 2021/10/12
- [PATCH v4 45/48] tcg/s390: Support raising sigbus for user-only, Richard Henderson, 2021/10/12
- [PATCH v4 46/48] tcg/tci: Support raising sigbus for user-only, Richard Henderson, 2021/10/12
- [PATCH v4 47/48] tcg/riscv: Support raising sigbus for user-only, Richard Henderson, 2021/10/12
- [PATCH v4 48/48] tests/tcg/multiarch: Add sigbus.c,
Richard Henderson <=