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[PATCH v2 06/13] target/riscv: Use REQUIRE_64BIT in amo_check64
From: |
Richard Henderson |
Subject: |
[PATCH v2 06/13] target/riscv: Use REQUIRE_64BIT in amo_check64 |
Date: |
Wed, 13 Oct 2021 13:50:57 -0700 |
Use the same REQUIRE_64BIT check that we use elsewhere,
rather than open-coding the use of is_32bit.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/insn_trans/trans_rvv.c.inc | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index fa451938f1..bbc5c93ef1 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -743,7 +743,8 @@ static bool amo_check(DisasContext *s, arg_rwdvm* a)
static bool amo_check64(DisasContext *s, arg_rwdvm* a)
{
- return !is_32bit(s) && amo_check(s, a);
+ REQUIRE_64BIT(s);
+ return amo_check(s, a);
}
GEN_VEXT_TRANS(vamoswapw_v, 0, rwdvm, amo_op, amo_check)
--
2.25.1
- [PATCH v2 02/13] target/riscv: Create RISCVMXL enumeration, (continued)
- [PATCH v2 02/13] target/riscv: Create RISCVMXL enumeration, Richard Henderson, 2021/10/13
- [PATCH v2 01/13] target/riscv: Move cpu_get_tb_cpu_state out of line, Richard Henderson, 2021/10/13
- [PATCH v2 03/13] target/riscv: Split misa.mxl and misa.ext, Richard Henderson, 2021/10/13
- [PATCH v2 05/13] target/riscv: Add MXL/SXL/UXL to TB_FLAGS, Richard Henderson, 2021/10/13
- [PATCH v2 06/13] target/riscv: Use REQUIRE_64BIT in amo_check64,
Richard Henderson <=
- [PATCH v2 04/13] target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl, Richard Henderson, 2021/10/13
- [PATCH v2 09/13] target/riscv: Replace DisasContext.w with DisasContext.ol, Richard Henderson, 2021/10/13