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[PATCH v5 19/67] hw/core: Add TCGCPUOps.record_sigsegv
From: |
Richard Henderson |
Subject: |
[PATCH v5 19/67] hw/core: Add TCGCPUOps.record_sigsegv |
Date: |
Thu, 14 Oct 2021 21:10:05 -0700 |
Add a new user-only interface for updating cpu state before
raising a signal. This will replace tlb_fill for user-only
and should result in less boilerplate for each guest.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/hw/core/tcg-cpu-ops.h | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h
index 6cbe17f2e6..41718b695b 100644
--- a/include/hw/core/tcg-cpu-ops.h
+++ b/include/hw/core/tcg-cpu-ops.h
@@ -111,6 +111,32 @@ struct TCGCPUOps {
*/
bool (*io_recompile_replay_branch)(CPUState *cpu,
const TranslationBlock *tb);
+#else
+ /**
+ * record_sigsegv:
+ * @cpu: cpu context
+ * @addr: faulting guest address
+ * @access_type: access was read/write/execute
+ * @maperr: true for invalid page, false for permission fault
+ * @ra: host pc for unwinding
+ *
+ * We are about to raise SIGSEGV with si_code set for @maperr,
+ * and si_addr set for @addr. Record anything further needed
+ * for the signal ucontext_t.
+ *
+ * If the emulated kernel does not provide anything to the signal
+ * handler with anything besides the user context registers, and
+ * the siginfo_t, then this hook need do nothing and may be omitted.
+ * Otherwise, record the data and return; the caller will raise
+ * the signal, unwind the cpu state, and return to the main loop.
+ *
+ * If it is simpler to re-use the sysemu tlb_fill code, @ra is provided
+ * so that a "normal" cpu exception can be raised. In this case,
+ * the signal must be raised by the architecture cpu_loop.
+ */
+ void (*record_sigsegv)(CPUState *cpu, vaddr addr,
+ MMUAccessType access_type,
+ bool maperr, uintptr_t ra);
#endif /* CONFIG_SOFTMMU */
#endif /* NEED_CPU_H */
--
2.25.1
- [PATCH v5 15/67] linux-user/host/riscv: Populate host_signal.h, (continued)
- [PATCH v5 15/67] linux-user/host/riscv: Populate host_signal.h, Richard Henderson, 2021/10/15
- [PATCH v5 16/67] target/arm: Fixup comment re handle_cpu_signal, Richard Henderson, 2021/10/15
- [PATCH v5 20/67] linux-user: Add cpu_loop_exit_sigsegv, Richard Henderson, 2021/10/15
- [PATCH v5 11/67] linux-user/host/arm: Populate host_signal.h, Richard Henderson, 2021/10/15
- [PATCH v5 17/67] linux-user/host/riscv: Improve host_signal_write, Richard Henderson, 2021/10/15
- [PATCH v5 14/67] linux-user/host/mips: Populate host_signal.h, Richard Henderson, 2021/10/15
- [PATCH v5 19/67] hw/core: Add TCGCPUOps.record_sigsegv,
Richard Henderson <=
- [PATCH v5 21/67] target/alpha: Implement alpha_cpu_record_sigsegv, Richard Henderson, 2021/10/15
- [PATCH v5 24/67] target/cris: Make cris_cpu_tlb_fill sysemu only, Richard Henderson, 2021/10/15
- [PATCH v5 18/67] linux-user/signal: Drop HOST_SIGNAL_PLACEHOLDER, Richard Henderson, 2021/10/15
- [PATCH v5 31/67] target/nios2: Implement nios2_cpu_record_sigsegv, Richard Henderson, 2021/10/15
- [PATCH v5 22/67] target/arm: Use cpu_loop_exit_sigsegv for mte tag lookup, Richard Henderson, 2021/10/15
- [PATCH v5 35/67] target/riscv: Make riscv_cpu_tlb_fill sysemu only, Richard Henderson, 2021/10/15
- [PATCH v5 33/67] target/openrisc: Make openrisc_cpu_tlb_fill sysemu only, Richard Henderson, 2021/10/15
- [PATCH v5 30/67] target/mips: Make mips_cpu_tlb_fill sysemu only, Richard Henderson, 2021/10/15