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[PATCH v5 34/67] target/ppc: Implement ppc_cpu_record_sigsegv
From: |
Richard Henderson |
Subject: |
[PATCH v5 34/67] target/ppc: Implement ppc_cpu_record_sigsegv |
Date: |
Thu, 14 Oct 2021 21:10:20 -0700 |
Record DAR, DSISR, and exception_index. That last means
that we must exit to cpu_loop ourselves, instead of letting
exception_index being overwritten.
This is exactly what the user-mode ppc_cpu_tlb_fill does,
so simply rename it as ppc_cpu_record_sigsegv.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/ppc/cpu.h | 3 ---
target/ppc/internal.h | 9 +++++++++
target/ppc/cpu_init.c | 6 ++++--
target/ppc/user_only_helper.c | 15 +++++++++++----
4 files changed, 24 insertions(+), 9 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index baa4e7c34d..2242d57718 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1279,9 +1279,6 @@ extern const VMStateDescription vmstate_ppc_cpu;
/*****************************************************************************/
void ppc_translate_init(void);
-bool ppc_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
- MMUAccessType access_type, int mmu_idx,
- bool probe, uintptr_t retaddr);
#if !defined(CONFIG_USER_ONLY)
void ppc_store_sdr1(CPUPPCState *env, target_ulong value);
diff --git a/target/ppc/internal.h b/target/ppc/internal.h
index 55284369f5..339974b7d8 100644
--- a/target/ppc/internal.h
+++ b/target/ppc/internal.h
@@ -283,5 +283,14 @@ static inline void pte_invalidate(target_ulong *pte0)
#define PTE_PTEM_MASK 0x7FFFFFBF
#define PTE_CHECK_MASK (TARGET_PAGE_MASK | 0x7B)
+#ifdef CONFIG_USER_ONLY
+void ppc_cpu_record_sigsegv(CPUState *cs, vaddr addr,
+ MMUAccessType access_type,
+ bool maperr, uintptr_t ra);
+#else
+bool ppc_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
+ MMUAccessType access_type, int mmu_idx,
+ bool probe, uintptr_t retaddr);
+#endif
#endif /* PPC_INTERNAL_H */
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 6aad01d1d3..ec8da08f0b 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -9014,9 +9014,11 @@ static const struct SysemuCPUOps ppc_sysemu_ops = {
static const struct TCGCPUOps ppc_tcg_ops = {
.initialize = ppc_translate_init,
- .tlb_fill = ppc_cpu_tlb_fill,
-#ifndef CONFIG_USER_ONLY
+#ifdef CONFIG_USER_ONLY
+ .record_sigsegv = ppc_cpu_record_sigsegv,
+#else
+ .tlb_fill = ppc_cpu_tlb_fill,
.cpu_exec_interrupt = ppc_cpu_exec_interrupt,
.do_interrupt = ppc_cpu_do_interrupt,
.cpu_exec_enter = ppc_cpu_exec_enter,
diff --git a/target/ppc/user_only_helper.c b/target/ppc/user_only_helper.c
index aa3f867596..7ff76f7a06 100644
--- a/target/ppc/user_only_helper.c
+++ b/target/ppc/user_only_helper.c
@@ -21,16 +21,23 @@
#include "qemu/osdep.h"
#include "cpu.h"
#include "exec/exec-all.h"
+#include "internal.h"
-
-bool ppc_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
- MMUAccessType access_type, int mmu_idx,
- bool probe, uintptr_t retaddr)
+void ppc_cpu_record_sigsegv(CPUState *cs, vaddr address,
+ MMUAccessType access_type,
+ bool maperr, uintptr_t retaddr)
{
PowerPCCPU *cpu = POWERPC_CPU(cs);
CPUPPCState *env = &cpu->env;
int exception, error_code;
+ /*
+ * Both DSISR and the "trap number" (exception vector offset,
+ * looked up from exception_index) are present in the linux-user
+ * signal frame.
+ * FIXME: we don't actually populate the trap number properly.
+ * It would be easiest to fill in an env->trap value now.
+ */
if (access_type == MMU_INST_FETCH) {
exception = POWERPC_EXCP_ISI;
error_code = 0x40000000;
--
2.25.1
- [PATCH v5 24/67] target/cris: Make cris_cpu_tlb_fill sysemu only, (continued)
- [PATCH v5 24/67] target/cris: Make cris_cpu_tlb_fill sysemu only, Richard Henderson, 2021/10/15
- [PATCH v5 18/67] linux-user/signal: Drop HOST_SIGNAL_PLACEHOLDER, Richard Henderson, 2021/10/15
- [PATCH v5 31/67] target/nios2: Implement nios2_cpu_record_sigsegv, Richard Henderson, 2021/10/15
- [PATCH v5 22/67] target/arm: Use cpu_loop_exit_sigsegv for mte tag lookup, Richard Henderson, 2021/10/15
- [PATCH v5 35/67] target/riscv: Make riscv_cpu_tlb_fill sysemu only, Richard Henderson, 2021/10/15
- [PATCH v5 33/67] target/openrisc: Make openrisc_cpu_tlb_fill sysemu only, Richard Henderson, 2021/10/15
- [PATCH v5 30/67] target/mips: Make mips_cpu_tlb_fill sysemu only, Richard Henderson, 2021/10/15
- [PATCH v5 34/67] target/ppc: Implement ppc_cpu_record_sigsegv,
Richard Henderson <=
- [PATCH v5 36/67] target/s390x: Use probe_access_flags in s390_probe_access, Richard Henderson, 2021/10/15
- [PATCH v5 37/67] target/s390x: Implement s390_cpu_record_sigsegv, Richard Henderson, 2021/10/15
- [PATCH v5 38/67] target/sh4: Make sh4_cpu_tlb_fill sysemu only, Richard Henderson, 2021/10/15
- [PATCH v5 23/67] target/arm: Implement arm_cpu_record_sigsegv, Richard Henderson, 2021/10/15
- [PATCH v5 25/67] target/hexagon: Remove hexagon_cpu_tlb_fill, Richard Henderson, 2021/10/15
- [PATCH v5 26/67] target/hppa: Make hppa_cpu_tlb_fill sysemu only, Richard Henderson, 2021/10/15
- [PATCH v5 28/67] target/m68k: Make m68k_cpu_tlb_fill sysemu only, Richard Henderson, 2021/10/15
- [PATCH v5 32/67] linux-user/openrisc: Adjust signal for EXCP_RANGE, EXCP_FPE, Richard Henderson, 2021/10/15