[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH v8 10/78] target/riscv: rvv-1.0: add vlenb register
From: |
frank . chang |
Subject: |
[PATCH v8 10/78] target/riscv: rvv-1.0: add vlenb register |
Date: |
Fri, 15 Oct 2021 15:45:11 +0800 |
From: Greentime Hu <greentime.hu@sifive.com>
Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_bits.h | 1 +
target/riscv/csr.c | 7 +++++++
2 files changed, 8 insertions(+)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index b8816822b81..849b100b3b7 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -63,6 +63,7 @@
#define CSR_VCSR 0x00f
#define CSR_VL 0xc20
#define CSR_VTYPE 0xc21
+#define CSR_VLENB 0xc22
/* VCSR fields */
#define VCSR_VXSAT_SHIFT 0
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 57591753059..0fb71875654 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -275,6 +275,12 @@ static RISCVException read_vl(CPURISCVState *env, int
csrno,
return RISCV_EXCP_NONE;
}
+static int read_vlenb(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ *val = env_archcpu(env)->cfg.vlen >> 3;
+ return RISCV_EXCP_NONE;
+}
+
static RISCVException read_vxrm(CPURISCVState *env, int csrno,
target_ulong *val)
{
@@ -1555,6 +1561,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_VCSR] = { "vcsr", vs, read_vcsr, write_vcsr },
[CSR_VL] = { "vl", vs, read_vl },
[CSR_VTYPE] = { "vtype", vs, read_vtype },
+ [CSR_VLENB] = { "vlenb", vs, read_vlenb },
/* User Timers and Counters */
[CSR_CYCLE] = { "cycle", ctr, read_instret },
[CSR_INSTRET] = { "instret", ctr, read_instret },
--
2.25.1
- Re: [PATCH v8 01/78] target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvh, (continued)
- [PATCH v8 02/78] target/riscv: drop vector 0.7.1 and add 1.0 support, frank . chang, 2021/10/15
- [PATCH v8 03/78] target/riscv: Use FIELD_EX32() to extract wd field, frank . chang, 2021/10/15
- [PATCH v8 04/78] target/riscv: rvv-1.0: add mstatus VS field, frank . chang, 2021/10/15
- [PATCH v8 05/78] target/riscv: rvv-1.0: add sstatus VS field, frank . chang, 2021/10/15
- [PATCH v8 06/78] target/riscv: rvv-1.0: introduce writable misa.v field, frank . chang, 2021/10/15
- [PATCH v8 07/78] target/riscv: rvv-1.0: add translation-time vector context status, frank . chang, 2021/10/15
- [PATCH v8 08/78] target/riscv: rvv-1.0: remove rvv related codes from fcsr registers, frank . chang, 2021/10/15
- [PATCH v8 09/78] target/riscv: rvv-1.0: add vcsr register, frank . chang, 2021/10/15
- [PATCH v8 10/78] target/riscv: rvv-1.0: add vlenb register,
frank . chang <=
- [PATCH v8 12/78] target/riscv: rvv-1.0: remove MLEN calculations, frank . chang, 2021/10/15
- [PATCH v8 11/78] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers, frank . chang, 2021/10/15
- [PATCH v8 13/78] target/riscv: rvv-1.0: add fractional LMUL, frank . chang, 2021/10/15
- [PATCH v8 15/78] target/riscv: rvv-1.0: update check functions, frank . chang, 2021/10/15
- [PATCH v8 16/78] target/riscv: introduce more imm value modes in translator functions, frank . chang, 2021/10/15
- [PATCH v8 18/78] target/riscv: rvv-1.0: remove amo operations instructions, frank . chang, 2021/10/15
- [PATCH v8 14/78] target/riscv: rvv-1.0: add VMA and VTA, frank . chang, 2021/10/15
- [PATCH 18/76] target/riscv: rvv-1.0: configure instructions, frank . chang, 2021/10/15
- [PATCH v8 17/78] target/riscv: rvv:1.0: add translation-time nan-box helper function, frank . chang, 2021/10/15